AD4003_17 Datasheet, PDF (29/38 Pages) Analog Devices – Precision, Differential SAR ADCs

Data Sheet
CS MODE, 3-WIRE TURBO MODE
This mode is typically used when a single AD4003/AD4007/
AD4011 device is connected to an SPI-compatible digital host. It
provides additional time during the end of the ADC conversion
process to clock out the previous conversion result, providing a
lower SCK rate. The AD4003 can achieve a throughput rate of
2 MSPS only when turbo mode is enabled and using a minimum
SCK rate of 75 MHz. With turbo mode enabled, the AD4007 can
also achieve its maximum throughput rate of 1 MSPS with a
minimum SCK rate of 25 MHz, and the AD4011 can achieve its
maximum throughput rate of 500 kSPS with a minimum SCK
rate of 11 MHz. The connection diagram is shown in Figure 53,
and the corresponding timing diagram is shown in Figure 54.
This mode replaces the 3-wire with busy indicator mode by
programming the turbo mode bit, Bit 1 (see Table 14).
AD4003/AD4007/AD4011
When SDI is forced high, a rising edge on CNV initiates a
conversion. The previous conversion data is available to read
after the CNV rising edge. The user must wait tQUIET1 time after
CNV is brought high before bringing CNV low to clock out the
previous conversion result. The user must also wait tQUIET2 time
after the last falling edge of SCK to when CNV is brought high.
When the conversion is complete, the AD4003/AD4007/AD4011
enter the acquisition phase and power down. When CNV goes
low, the MSB is output to SDO. The remaining data bits are
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 18^th SCK
falling edge or when CNV goes high (whichever occurs first),
SDO returns to high impedance.
SDI = 1
VIO
SDI
CNV
AD4003/
AD4007/ SDO
AD4011
SCK
CONVERT
DIGITAL HOST
DATA IN
CLK
Figure 53. CS Mode, 3-Wire Turbo Mode Connection Diagram (SDI High)
t_CYC
CNV
ACQUISITION
SCK
t_QUIET1
SDO
CONVERSION
CONV
1
2
t_EN
D17
D16
t_ACQ
ACQUISITION
t_SCKL
t_SCK
3
16
t_HSDO
t_DSDO
17
18
t_SCKH
D15
D1
D0
Figure 54. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (SDI High)
QUIET2
t_DIS
Rev. B | Page 29 of 38