AD4003_17 Datasheet, PDF (1/38 Pages) Analog Devices – Precision, Differential SAR ADCs

Data Sheet
18-Bit, 2 MSPS/1 MSPS/500 kSPS,
Precision, Differential SAR ADCs
AD4003/AD4007/AD4011
FEATURES
GENERAL DESCRIPTION
Throughput: 2 MSPS/1 MSPS/500 kSPS options
The AD4003/AD4007/AD4011 are low noise, low power, high
INL: ±1.0 LSB (±3.8 ppm) maximum
speed, 18-bit, precision successive approximation register (SAR)
Guaranteed 18-bit no missing codes
analog-to-digital converters (ADCs). The AD4003, AD4007, and
Low power
AD4011 offer 2 MSPS, 1 MSPS, and 500 kSPS throughputs,
9.5 mW at 2 MSPS, 4.9 mW at 1 MSPS, 2.4 mW at 500 kSPS
respectively. They incorporate ease of use features that reduce
(VDD only)
signal chain power consumption, reduce signal chain complexity,
80 μW at 10 kSPS, 16 mW at 2 MSPS (total)
and enable higher channel density. The high-Z mode, coupled with
SNR: 100.5 dB typical at 1 kHz, VREF = 5 V; 99 dB typical at
a long acquisition phase, eliminates the need for a dedicated high
100 kHz
power, high speed ADC driver, thus broadening the range of low
THD: −123 dB typical at 1 kHz, VREF = 5 V; −100 dB typical at
power precision amplifiers that can drive these ADCs directly while
100 kHz
still achieving optimum performance. The input span compression
Ease of use features reduce system power and complexity
feature enables the ADC driver amplifier and the ADC to operate
Input overvoltage clamp circuit
off common supply rails without the need for a negative supply
Reduced nonlinear input charge kickback
while preserving the full ADC code range. The low serial
High-Z mode
peripheral interface (SPI) clock rate requirement reduces the digital
Long acquisition phase
input/output power consumption, broadens processor options, and
Input span compression
simplifies the task of sending data across digital isolation.
Fast conversion time allows low SPI clock rates
Operating from a 1.8 V supply, the AD4003/AD4007/AD4011 have
SPI-programmable modes, read/write capability, status word
Differential analog input range: ±VREF
a ±VREF fully differential input range with VREF ranging from 2.4 V
to 5.1 V. The AD4003 consumes only 16 mW at 2 MSPS with a
0 V to VREF with VREF from 2.4 V to 5.1 V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
SAR architecture: no latency/pipeline delay, valid first
conversion
First conversion accurate
Guaranteed operation: −40°C to +125°C
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
Ability to daisy-chain multiple ADCs and busy indicator
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
APPLICATIONS
Automatic test equipment
Machine automation
Medical equipment
Battery-powered equipment
Precision data acquisition systems
minimum SCK rate of 75 MHz in turbo mode, the AD4007
consumes only 8 mW at 1 MSPS, and the AD4011 consumes only 4
mW at 500 kSPS. The AD4003/AD4007/AD4011 all achieve ±1.0
LSB integral nonlinearty error (INL) maximum, guaranteed no
missing codes at 18 bits with 100.5 dB typical signal-to-noise ratio
(SNR) for 1 kHz inputs. The reference voltage is applied externally
and can be set independently of the supply voltage.
The SPI-compatible versatile serial interface features seven different
modes including the ability, using the SDI input, to daisy-chain
several ADCs on a single 3-wire bus and provides an optional busy
indicator. The AD4003/AD4007/AD4011 are compatible with 1.8
V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply.
The AD4003/AD4007 are available in a 10-lead MSOP and LFCSP,
and the AD4011 is available in a 10-lead LFCSP, with operation
specified from −40°C to +125°C. The devices are pin compatible
with the 16-bit, 2 MSPS AD4000 (see Table 8).
FUNCTIONAL BLOCK DIAGRAM
2.5V TO 5V
10µF
1.8V
V_REF
V_REF/2
0
V_REF
V_REF/2
0
AD4003/
AD4007/
IN+ ^AD4011
IN–
CLAMP
REF
VDD
HIGH-Z
MODE
18-BIT
SAR ADC
SPAN
COMPRESSION
TURBO
MODE
SERIAL
INTERFACE
STATUS
BITS
GND
VIO _{1.8V TO 5V}
SDI
SCK
SDO
CNV
3-WIRE OR 4-WIRE
SPI INTERFACE
(DAISY CHAIN, CS)
Figure 1.
Rev. B
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