ADSP-BF707 Datasheet, PDF (28/85 Pages) –

Housekeeping ADC
Housekeeping ADC
The ADSP-BF707 processor provides four housekeeping ADC inputs:
HADC0_VIN0 through HADC_VIN3. The EZ-KIT Lite connects HADC0_VIN0 to
pin 2 of a four position 0.1” header (JP1). JP1 has VDD_RTC voltage domain
on pin 1, allowing a jumper to connect the voltage back to the processor.
Pin 4 of JP1 connects through an RC timer to HADC0_VIN1.
HADC_VIN2 and HADC_VIN3 are connected to SMC connectors (J7 and J8).
Refer to ADSP-BF707 EZ-KIT Lite Schematic for more information.
UART0 Interface
The ADSP-BF707 processor has two built-in universal asynchronous
transmitters (UARTs). UART0 is connected to an FTDI, FT232RQ, USB
to UART converter IC (U45).
The UART functionality is connected by default through SoftConfig.
Refer to Software-Controlled Switches (SoftConfig) for more
information.
For more information, refer to the UART0 example in the POST, which
is included in the ADSP-BF707 Board Support Package.
CAN0 Interface
The Controller Area Network 0 (CAN0) interface of the EZ-KIT Lite is
connected to the NXP TJA1041 CAN transceiver (U46). The transceiver is
attached to the CAN0 port of the ADSP-BF707processor via an RJ-11 con-
nector (J4). See CAN0 Connector (J4).
The CAN0 transmit, receive, and error signals are connected through the
SoftConfig switches and disabled by default. CAN0_EN is enabled by default
and CAN0_STB is disabled. See Software-Controlled Switches (SoftConfig).
1-10
ADSP-BF707 EZ-KIT Lite Evaluation System Manual