ADSP-21371 Datasheet, PDF (28/48 Pages) Analog Devices – SHARC Processor

ADSP-21371
Preliminary Technical Data
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, data channel A, data channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 25. Serial Ports—External Clock
Parameter
Timing Requirements
t_SFSE¹
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
t_HFSE¹
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
t_SDRE¹
t_HDRE¹
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
t_SCLKW
SCLK Width
t_SCLK
SCLK Period
Switching Characteristics
t_DFSE²
FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
t_HOFSE²
FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
t_DDTE²
t_HDTE²
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
1 _{Referenced to sample edge.}
2 _{Referenced to drive edge.}
Min
Max
Unit
2.5
ns
2.5
ns
2.5
ns
2.5
ns
15
ns
30
ns
7
ns
2
ns
7
ns
2
ns
Table 26. Serial Ports—Internal Clock
Parameter
Timing Requirements
t_SFSI¹
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
t_HFSI¹
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
t_SDRI¹
t_HDRI¹
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
Switching Characteristics
t_DFSI²
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
t_HOFSI²
t_DFSI²
t_HOFSI²
t_DDTI²
t_HDTI²
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
FS Delay After SCLK (Internally Generated FS in Receive or Mode)
FS Hold After SCLK (Internally Generated FS in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
t_SCLKIW
Transmit or Receive SCLK Width
1 _{Referenced to the sample edge.}
2 _{Referenced to drive edge.}
Min
Max
Unit
7
2.5
7
2.5
–1.0
–1.0
–1.0
0.5t_SCLK – 2
ns
ns
ns
ns
3
ns
ns
3
ns
ns
3
ns
ns
0.5t_SCLK + 2
ns
Rev. PrA | Page 28 of 48 | June 2006