ADSP-21371 Datasheet, PDF (13/48 Pages) Analog Devices – SHARC Processor

Preliminary Technical Data
ADSP-21371
Table 5. Pin List
Name
FLAG[1]/IRQ1
FLAG[2]/IRQ2/
MS2
FLAG[3]/TIMEXP/M
S3
TDI
TDO
TMS
TCK
TRST
EMU
CLK_CFG_1–0
Type
I/O
I/O
State During
and After Reset
High-Z/high-Z
High-Z/high-Z
I/O with programma- High-Z/high-Z
ble pu (for MS mode)
Input with program-
mable pu (for MS
mode)
O (pu)
I
I (pu)
I
O (pu)
I (pu)
Description
FLAG1/Interrupt Request1.
FLAG2/Interrupt Request/Memory Select2.
FLAG3/Timer Expired/Memory Select3.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 kΩ internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
internal pull-up resistor.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed
low) after power-up or held low for proper operation of the ADSP-21371.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the ADSP-21371. TRST has a 22.5 kΩ internal
pull-up resistor.
Emulation Status. Must be connected to the ADSP-21371 Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ internal
pull-up resistor.
Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 8 for a
description of the clock configuration modes.
BOOT_CFG_1–0
I
RESET
I
XTAL
O
CLKIN
I
CLKOUT
O/T
Driven low/
driven high
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
Boot Configuration Select. These pins select the boot mode for the processor. The
BOOTCFG pins must be valid before reset is asserted. See Table 7 for a description of the
boot modes.
Processor Reset. Resets the ADSP-21371 to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted (low)
at power-up.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21371 clock input. It
configures the ADSP-21371 to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the ADSP-21371 to use the external clock source such as an external clock
oscillator. CLKIN may not be halted, changed, or operated below the specified frequency.
Local Clock Out. CLKOUT can also be configured as a reset out pin.The functionality can
be switched between the PLL output clock and reset out by setting bit 12 of the PMCTREG
register. The default is reset out.
1 _{Pull-up can be enabled/disabled, value of pull-up cannot be programmed.}
Rev. PrA | Page 13 of 48 | June 2006