ADV7189 Datasheet, PDF (27/104 Pages) Analog Devices – Multiformat SDTV Video Decoder

SDP CLAMP OPERATION
FINE
CURRENT
SOURCES
COARSE
CURRENT
SOURCES
ADV7189
ANALOG
VIDEO
INPUT
ADC
DATA
PRE
PROCESSOR
(DPP)
SDP
WITH DIGITAL
FINE CLAMP
CLAMP CONTROL
Figure 10. SDP Clamping Overview
The input video is ac-coupled into the ADV7189. Therefore its
dc value needs to be restored. This process is referred to as
clamping the video. This section explains the general process of
clamping on the ADV7189 for the SDP and shows the different
ways in which a user can configure its behavior.
The SDP block uses a combination of current sources and a
digital processing block for clamping, as shown in Figure 10.
The analog processing channel shown is replicated three times
inside the IC. While only one single channel (and only one
ADC) would be needed for a CVBS signal, two independent
channels are needed for YC (S-VHS) type signals, and three
independent channels are needed to allow component signals
(YPrPb) to be processed.
The clamping can be divided into two sections:
• Clamping before the ADC (analog domain): current
sources.
The clamping scheme has to complete two tasks: it must be able
to acquire a newly connected video signal with a completely
unknown dc level, and it must maintain the dc level during
normal operation.
For a fast acquiring of an unknown video signal, the large
current clamps may be activated⁷. Control of the coarse and fine
current clamp parameters is performed automatically by the
decoder.
Standard definition video signals may have excessive noise on
them. In particular, CVBS signals transmitted by terrestrial
broadcast and demodulated using a tuner usually show very
large levels of noise (>100 mV). A voltage clamp would be
unsuitable for this type of video signal. Instead, the ADV7189
employs a set of four current sources that can cause coarse
(>0.5 mA) and fine (<0.1 mA) currents to flow into and away
from the high impedance node that carries the video signal (see
Figure 10).
• Clamping after the ADC (digital domain): digital
processing block.
The following sections describe the I²C signals that can be used
to influence the behavior of SDP clamping.
The ADCs can digitize an input signal only if it resides within
the ADC’s 1.6 V input voltage range. An input signal with a dc
level that is too large or too small is clipped at the top or bottom
of the ADC range.
The primary task of the analog clamping circuits is to ensure
that the video signal stays within the valid ADC input window
so the analog to digital conversion can take place. It is not nec-
essary to clamp the input signal with a very high accuracy in the
analog domain as long as the video signal fits the ADC range.
After digitization, the digital fine clamp block corrects for any
remaining variations in dc level. Since the dc level of an input
video signal refers directly to the brightness of the picture
transmitted, it is important to perform a fine clamp with high
accuracy; otherwise, brightness variations may occur.
Furthermore, dynamic changes in the dc level will almost
certainly lead to visually objectionable artifacts, and must
therefore be prohibited.
Previous revisions of the ADV7189 had controls (FACL/FICL,
fast and fine clamp length) to allow configuration of the length
for which the coarse (fast) and fine current sources are switched
on. These controls were removed on the ADV7189-FT and
replaced by an adaptive scheme.
CCLEN Current Clamp Enable (SDP), Address 0x14, [4]
The current clamp enable bit allows the user to switch off the
current sources in the analog front end altogether. This may be
useful if the incoming analog video signal is clamped externally.
Table 56. CCLEN Function
CCLEN
Description
0
Current sources switched off.
1*
Current sources enabled.
*Default value.
7 _{It is assumed that the amplitude of the video signal at this point is of a}
nominal value.
Rev. A | Page 27 of 104