ADV7189 Datasheet, PDF (16/104 Pages) Analog Devices – Multiformat SDTV Video Decoder

ADV7189
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVE MODES
Power-Down
PDBP, Address 0x0F, [2]
There are two ways to shut down the digital core of the
ADV7189: a pin (PWRDN) and a bit (PWRDN see below). The
PDBP controls which of the two has the higher priority. The
default is to give the pin (PWRDN) priority. This allows the
user to have the ADV7189 powered down by default.
Table 11. PDBP Function
PDBP Description
0*
Digital core power controlled by the PWRDN pin (bit is
disregarded).
1
Bit has priority (pin is disregarded).
*Default value.
PWRDN, Address 0x0F, [5]
Setting the PWRDN bit switches the ADV7189 into a chip-wide
power-down mode. The power-down stops the clock from
entering the digital section of the chip, thereby freezing its
operation. No I²C bits are lost during power-down. The
PWRDN bit also affects the analog blocks and switches them
into low current modes. The I²C interface itself is unaffected,
and remains operational in power-down mode.
The ADV7189 leaves the power-down state if the PWRDN bit is
set to 0 (via I²C), or if the overall part is reset using Pin RESET.
Note that PDBP must be set to 1 for the PWRDN bit to power
down the ADV7189.
Table 12. PWRDN Function
PWRDN
Description
0*
Chip operational.
1
ADV7189 in chip-wide power-down.
*Default value.
ADC Power-Down Control
The ADV7189 contains three 12-bit ADCs (ADC 0, ADC 1, and
ADC 2). If required, it is possible to power down each ADC
individually.
When should the ADCs be powered down?
• CVBS mode. ADC 1 and ADC 2 should be powered down
to save on power consumption.
• S-Video mode. ADC 2 should be powered down to save on
power consumption.
PWRDN_ADC_0, Address 0x3A, [3]
Table 13. PWRDN_ADC_0 Function
PWRDN_ADC_0
Description
0*
ADC normal operation.
1
Power down ADC 0.
*Default value.
PWRDN_ADC_1, Address 0x3A, [2]
Table 14. PWRDN_ADC_1 Function
PWRDN_ADC_1 Description
0*
ADC normal operation.
1
Power down ADC 1.
*Default value.
PWRDN_ADC_2, Address 0x3A, [1]
Table 15. PWRDN_ADC_2 Function
PWRDN_ADC_2
Description
0*
1
*Default value.
ADC normal operation.
Power down ADC 2.
RESET CONTROL
Chip Reset (RES), Address 0x0F, [7]
Setting this bit, equivalent to controlling the RESET pin on the
ADV7189, issues a full chip reset. All I²C registers get reset to
their default values⁶. After the reset sequence, the part immedi-
ately starts to acquire the incoming video signal.
Notes
• After setting the RES bit (or initiating a reset via the pin),
the part returns to the default mode of operation with
respect to its primary mode of operation. All I²C bits are
loaded with their default values, making this bit self-
clearing.
• Executing a software reset takes approximately 2 ms.
However, it is recommended to wait 5 ms before any
further I²C writes are performed.
• The I²C master controller receives a no acknowledge
condition on the ninth clock cycle when Chip Reset is
implemented (see the MPU Port Description section for a
full description).
Table 16. RES Function
RES
Description
0*
Normal operation.
1
Start reset sequence.
*Default value.
6 _{Some register bits do not have a reset value specified. They keep their last}
written value. Those bits are marked as having a reset value of x in the
register table.
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