ADSP-TS101S_09 Datasheet, PDF (27/48 Pages) Analog Devices – TigerSHARC Embedded Processor

ADSP-TS101S
Table 28. AC Signal Specifications (for 16.7 ns <SCLK <25 ns) (All values in this table are in nanoseconds) (Continued)
Name
RESET^{4, 7}
TMS⁴
TDI⁴
TDO
TRST^{4, 7, 9}
BM⁵
EMU¹⁰
JTAG_SYS_IN¹¹
JTAG_SYS_OUT¹²
ID2–0⁹
CONTROLIMP2–0⁹
DS2–0⁹
LCLKRAT2–0⁹
SCLKFREQ⁹
Description
Global Reset
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Data Output (JTAG)
Test Reset (JTAG)
Bus Master Debug Aid Only
Emulation
System Input
System Output
Chip ID—Must Be Constant
Static Pins—Must Be Constant
Static Pins—Must Be Constant
Static Pins—Must Be Constant
Static Pins—Must Be Constant
SCLK
1.5
1.0
TCK
1.5
1.0
TCK
6.0
1.0
1.0
5.0
TCK_FE⁸
TCK
4.2
0.8
SCLK
5.5
5.0
TCK or LCLK
1.5
11.0
TCK
16.0
TCK_FE⁸
1 _{The output valid (max) value in this column applies for the standard 30 pF capacitive load used in testing. To see how output valid varies with capacitive loading, see Figure 40}
on Page 36.
2 _{The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The}
apparent driver overlap, due to output disables being larger than output enables, is not actual.
3 _{CPA and DPA pins are open drains and have 0.5 k internal pull-ups.}
4 _{These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. These synchronous specifications only apply for recognition in the}
current clock reference cycle.
5 _{This pin is a strap option. During reset, an internal resistor pulls the pin low.}
6 _{For input specifications, see Table 21.}
7 _{For additional requirement details, see Reset and Booting on Page 9.}
8 _{TCK_FE indicates TCK falling edge.}
9 _{These pins may change only during reset; recommend connecting it to VDD_IO/VSS.}
10_{Reference clock depends on function.}
11_{System inputs are: IRQ3–0, BMS, LCLKRAT2–0, SCLKFREQ, BM, TMR0E, FLAG3–0, ID2–0, BRST, WRH, WRL, RD, MSSD, SDCKE, SDWE, CAS, RAS, ADDR31–0,}
DATA63–0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7–0, L0CLKIN, L0DAT7–0, L1CLKIN, L1DAT7–0, L2CLKIN, L2DAT7–0, L2DIR, L3CLKIN, L3DAT7–0, DS2–0,
CONTROLIMP2–0, RESET, DMAR3–0.
12_{System outputs are: BMS, BM, BUSLOCK, TMR0E, FLAG3–0, FLYBY, IOEN, MSH, BRST, WRH, WRL, RD, MS1–0, HDQM, LDQM, MSSD, SDCKE, SDWE, CAS, RAS,}
ADDR31–0, DATA63–0, DPA, CPA, HBG, ACK, BR7–0, L0CLKOUT, L0DAT7–0, L0DIR, L1CLKOUT, L1DAT7–0, L1DIR, L2CLKOUT, L2DAT7–0, L2DIR, L3CLKOUT,
L3DAT7–0, L3DIR, EMU.
Rev. C | Page 27 of 48 | May 2009