ADSP-TS101S_09 Datasheet, PDF (1/48 Pages) Analog Devices – TigerSHARC Embedded Processor

FEATURES
300 MHz, 3.3 ns instruction cycle rate
6M bits of internal—on-chip—SRAM memory
19 mm × 19 mm (484-ball) or 27 mm × 27 mm
(625-ball) PBGA package
Dual computation blocks—each containing an ALU, a multi-
plier, a shifter, and a register file
Dual integer ALUs, providing data addressing and pointer
manipulation
Integrated I/O includes 14-channel DMA controller, external
port, 4 link ports, SDRAM controller, programmable flag
pins, 2 timers, and timer expired pin for system integration
1149.1 IEEE compliant JTAG test access port for on-chip
emulation
On-chip arbitration for glueless multiprocessing with up to
8 TigerSHARC processors on a bus
TigerSHARC
Embedded Processor
ADSP-TS101S
BENEFITS
Provides high performance Static Superscalar DSP opera-
tions, optimized for telecommunications infrastructure
and other large, demanding multiprocessor DSP
applications
Performs exceptionally well on DSP algorithm and I/O bench-
marks (see benchmarks in Table 1 and Table 2)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, other DSPs (multiprocessor), and host
processors
Eases DSP programming through extremely flexible instruc-
tion set and high-level language-friendly DSP architecture
Enables scalable multiprocessing systems with low commu-
nications overhead
COMPUTATIONAL BLOCKS
SHIFTER
ALU
MULTIPLIER
X
REGISTER
FILE
32 × 32
128 128
DAB
DAB
128 128
Y
REGISTER
FILE
32 × 32
MULTIPLIER
ALU
SHIFTER
PROGRAM SEQUENCER
PC BTB IRQ
ADDR
IAB
FETCH
DATA ADDRESS GENERATION
INTEGER ³²
J ALU
32 × 32
32 _INTEGER
K ALU
32 × 32
32
128
32
128
32
128
I/O PROCESSOR
DMA
CONTROLLER
CONTROL/
STATUS/
TCBs
DMA ADDRESS
DMA DATA
INTERNAL MEMORY
MEMORY MEMORY MEMORY
M0
M1
M2
64K × 32 64K × 32 64K × 32
A
DA
DA
D
6
JTAG PORT
SDRAM CONTROLLER
32 256
M0 ADDR
M0 DATA
M1 ADDR
M1 DATA
EXTERNAL PORT
MULTIPROCESSOR
INTERFACE
HOST INTERFACE
INPUT FIFO
32
ADDR
64
OUTPUT BUFFER
DATA
M2 ADDR
M2 DATA
I/O ADDRESS 32
OUTPUT FIFO
CLUSTER BUS
ARBITER
CNTRL
3
LINK PORT
CONTROLLER
L0
8
3
256
LINK DATA
L1
8
LINK
PORTS
3
CONTROL/
STATUS/
BUFFERS
L2
8
3
L3
8
Figure 1. Functional Block Diagram
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
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