ADSP-21375 Datasheet, PDF (27/42 Pages) Analog Devices – SHARC Processor

Preliminary Technical Data
ADSP-21375
Memory Read – Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 21. Memory Read – Bus Master
Parameter
Min
Timing Requirements
t_DAD
Address, Selects Delay to Data Valid^{1, 2}
t_DRLD
RD Low to Data Valid¹
t_SDS
Data Setup to RD High
1.79
t_HDRH
Data Hold from RD High^{3, 4}
0
t_DAAK
ACK Delay from Address, Selects^{2, 5}
t_DSAK
ACK Delay from RD Low⁴
t_HAKC
ACK Hold After RD High
0
Max
W+t_SDCLK – 5.12
W– 1.5 + t_SDCLK
t_SDCLK– 9.5 + W
W– 7.0
Unit
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
t_DRHA
Address Selects Hold After RD High
RH + 0.44
ns
t_DARL
Address Selects to RD Low²
t_SDCLK– 3.3
ns
t_RW
RD Pulsewidth
W – 0.5
ns
t_RWR
RD High to WR, RD, Low
HI +t_SDCLK
ns
W = (number of wait states specified in AMICTLx register) × t_SDCLK.
HI =RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) x t_SDCLK
IC = (number of Idle Cycles specified in AMICTLx register) x t_SDCLK).
H = (number of Hold Cycles specified in AMICTLx register) x t_SDCLK.
1 _{Data Delay/Setup: System must meet tDAD, tDRLD, or tSDS.}
2 _{The falling edge of MSx, is referenced.}
3 _{Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.}
4 _{Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Test Conditions on Page 39 for the calculation of hold times given capacitive and dc loads.}
5 _{ACK Delay/Setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK.}
ADDRESS
MSx
RD
DATA
ACK
t_DARL
t_DAAK
t_DAD
t_DRLD
t_{DSA K}
t_RW
t_SDS
t_HDA
t_DRHA
t_HDRH
t_HAKC
t_RWR
WR
Figure 14. Memory Read – Bus Master
Rev. PrB | Page 27 of 42 | December 2005