ADSP-21375 Datasheet, PDF (1/42 Pages) Analog Devices – SHARC Processor

a
Preliminary Technical Data
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—0.5M bit of on-chip SRAM and a dedicated
2M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21375 is available with a 266 MHz core instruction
rate with unique audio centric peripherals such as the digi-
tal applications interface, serial ports, precision clock
generators and more. For complete ordering information,
see Ordering Guide on Page 42
SHARC^® Processor
ADSP-21375
CORE PRO CESSOR
TI MER
INSTRUCTIO N
CACHE
32 X 48-BIT
DAG 1
8X 4X3 2
DAG2
8 X4X 32
P ROGRAM
SE QUENCER
P M A D D RE SS BU S 32
DM A DD R ES S B U S
32
PM DA TA B U S 6 4
DM DATA BUS ⁶⁴
PROCESS ING
E LE M ENT
(P EX)
PROCESS ING
ELE ME NT
(P EY)
PX REGISTER
4 BLOCKS O F
ON-CHIP MEMORY
0. 5M BIT RAM, 2M BIT ROM
JTAG T EST & EMULATION
ADDR
32
DATA
64
IO A(24)
FLAGS4 _-15
I OD(32)
EXTERNAL PORT
7
SDRAM
CO NTRO LLER
ASY NCHRONOUS
3
MEMO RY
INTERFACE
16
DATA
11
CONTROL
24
ADDRES S
IOP REGISTER (MEMORY MAPPED)
CONTRO L, STATUS, & DATA BUFFERS
DMA CONTROLLER
(24 CHANNELS )
MEMO RY-TO-MEMORY
DMA (2)
4 _{GP IO FLAGS/}
IRQ/TIM EX P
S
PRECISION CLO CK
GENERATORS (4)
SERIAL PORTS (4)
INPUT DATA POR T/
PDAP
DAI PINS
DIGITAL APPLICATIONS INTERFACE
20
SPI PORT (2)
TWO WIRE
INTERFACE
DPI PINS
UART (1)
TIMERS (2)
DIGITAL PERIP HERAL INTE RFACE
I/O PROCESSOR
14
Figure 1. Functional Block Diagram
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Rev. PrB
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