ADSP-21364 Datasheet, PDF (27/52 Pages) Analog Devices – SHARC Processor

Preliminary Technical Data
Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-21364 is accessing external memory space.
Table 22. 8-bit Memory Write Cycle
Parameter
Min
Switching Characteristics:
t_ALEW
t_ADAS¹
t_ALERW
ALE Pulse Width
Address/Data 15–0 Setup Before ALE Deasserted
ALE Deasserted to Read/Write Asserted
2 × t_PCLK – 2
t_PCLK – 2.5
2 × t_PCLK – 2
t_RWALE
t_WRH
t_ADAH¹
t_WW
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to next WR Falling Edge
Address/Data 15–0 Hold After ALE Deasserted
WR Pulse Width
H + 0.5
F + H + t_PCLK – 2
t_PCLK – 0.5
D–F–2
t_ADWL
t_ADWH
Address/Data 15–8 to WR Low
Address/Data 15–8 Hold After WR High
t_PCLK – 1.5
H
t_DWS
t_DWH
Address/Data 7–0 Setup Before WR High
Address/Data 7–0 Hold After WR High
D – F + t_PCLK – 4
H
t_DAWH
Address/Data to WR High
D – F + t_PCLK – 4
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t_PCLK
H = t_PCLK (if a hold cycle is specified, else H = 0)
F = 7 x t_PCLK (if FLASH_MODE is set else F = 0)
1 _{On reset, ALE is an active high cycle. However, it can be configured by software to be active low.}
ADSP-21364
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE
WR
RD
AD15-8
AD7-0
t_ALEW
t_ALERW
t_WW
t_RWALE
t_ADWL
t_DAWH
t_WRH
t_ADAS
t_ADAH
VALID
ADDRESS
VALID ADDRESS
VALID
ADDRESS
t_DWS
VALID DATA
t_ADWH
VALID ADDRESS
t_DWH
VALID DATA
Figure 19. Write Cycle For 8-Bit Memory Timing
Rev. PrB | Page 27 of 52 | September 2004