ADSP-1981BL_15 Datasheet, PDF (26/32 Pages) Analog Devices – AC 97 SoundMAX Codec

AD1981BL
EQ DATA REGISTER
Index 0x62
Reg
No.
0x62
Name
EQ
Data
D15
CFD15
D14
CFD14
D13
CFD13
D12
CFD12
D11
CFD11
D10
CFD10
D9
CFD9
D8
CFD8
D7
CFD7
D6
CFD6
D5
CFD5
D4
CFD4
D3
CFD3
D2
CFD2
D1
CFD1
D0
CFD0
Default
0x0000
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the BCA
bits in the EQ Cntrl Register (0x60). Data is written to memory only if the EQM bit (Register 0x60, Bit 15) is asserted.
Table 37.
Bit
CFD [15:0]
Mnemonic
Coefficient Data
Function
The biquad coefficients are fixed-point format values with 16 bits of resolution. The CFD15 bit is
the MSB, and the CFD0 bit is the LSB.
MIXER ADC, INPUT GAIN REGISTER
Index 0x64
Reg
No.
0x64
Name
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3
D2
D1
D0
Default
Mixer ADC, MXM X
X
X
LMG3 LMG2 LMG1 LMG0 RM¹ X X X RMG3 RMG2 RMG1 RMG0 0x8000
Volume
1 _{For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.}
If MSPLT is not set, the RM bit has no effect.
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 39 for examples.
Table 38.
Bit
RMG [3:0]
RM
LMG [3:0]
MXM
Mnemonic
Right Mixer Gain
Control
Right-Channel Mute
Left Mixer Gain Control
Mixer Gain Register
Mute
Function
This register controls the gain into the mixer ADC from 0 dB to a maximum gain of 22.5 dB. The
least significant bit represents 1.5 dB.
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from
the MXM bit. Otherwise, this bit always reads 0 and has no affect when set to 1.
This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of 22.5 dB. The
least significant bit represents 1.5 dB.
0 = Unmuted.
1 = Muted (reset default).
Table 39. Settings for Mixer ADC, Input Gain
Reg. 0x76
Control Bits Mixer ADC, Input Gain (0x64)
Left-Channel Mixer Gain D [11:8]
Right-Channel Mixer Gain D [3:0]
MSPLT¹ D15 Write Readback Function
D7¹ Write Readback Function
0
0 1111 1111
22.5 dB Gain
X 1111 1111
22.5 dB Gain
0
0 0000 0000
0 dB Gain
X 0000 0000
0 dB Gain
0
1 XXXX XXXX
−∞ dB Gain, Muted
X XXXX XXXX
−∞ dB Gain, Muted
1
0 1111 1111
22.5 dB Gain
1 XXXX XXXX
−∞ dB Gain, Right Only Muted
1
1 XXXX XXXX
−∞ dB Gain, Left Only Muted 0 1111 1111
22.5 dB Gain
1
1 XXXX XXXX
−∞ dB Gain, Left Muted
1 XXXX XXXX
−∞ dB Gain, Right Muted
1 _{For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.}
If MSPLT is not set, the RM bit has no effect.
X is a wild card, and has no effect on the value.
Rev. A | Page 26 of 32