ADSP-1981BL_15 Datasheet, PDF (23/32 Pages) Analog Devices – AC 97 SoundMAX Codec

AD1981BL
Bit
SPCV
VFORCE
Mnemonic
SPDIF Configuration Valid
(Read-Only)
Validity Force Bit
(Reset Default = 0)
Function
This bit indicates the status of the SPDIF transmitter subsystem, enabling the driver to
determine if the currently programmed SPDIF configuration is supported. SPCV is always valid,
independent of the SPDIF enable bit status.
SPCV = 0 indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not
valid (not supported).
SPCV = 1 indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid
(supported).
When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R
subframe) to be controlled by the V bit (D15) in Register 0x3A (SPDIF control register).
VFORCE = 0 and V = 0; the validity bit is managed by the codec error detection logic.
VFORCE = 0 and V = 1; the validity bit is forced high, indicating the subframe data is invalid.
VFORCE = 1 and V = 0; the validity bit is forced low, indicating the subframe data is valid.
VFORCE = 1 and V = 1; the validity bit is forced high, indicating the subframe data is invalid.
Table 32. AC ’97 2.2 AMAP-Compliant Default SPDIF Slot Assignments
Codec ID Function
SPSA = 00 SPSA = 01
00
2-Channel Primary w/SPDIF
3 and 4
7 and 8 (default)
00
4-Channel Primary w/SPDIF
3 and 4
7 and 8
00
6-Channel Primary w/SPDIF
3 and 4
7 and 8
01
+2-Channel Secondary w/SPDIF 3 and 4
7 and 8
01
+4-Channel Secondary w/SPDIF 3 and 4
7 and 8
10
+2-Channel Secondary w/SPDIF 3 and 4
7 and 8
10
+4-Channel Secondary w/SPDIF 3 and 4
7 and 8
11
+2-Channel Secondary w/SPDIF 3 and 4
7 and 8
SPSA = 10
6 and 9
6 and 9 (default)
6 and 9
6 and 9 (default)
6 and 9
6 and 9 (default)
6 and 9
6 and 9
SPSA = 11
10 and 11
10 and 11
10 and 11 (default)
10 and 11 (default)
10 and 11 (default)
10 and 11 (default)
PCM FRONT DAC RATE REGISTER
Index 0x2C
Reg
No.
0x2C
Name
PCM
Front
DAC
Rate
D15
SRF15
D14
SRF14
D13
SRF13
D12
SRF12
D11
SRF11
D10
SRF10
D9
SRF9
D8
SRF8
D7
SRF7
D6
SRF6
D5
SRF5
D4
SRF4
D3
SRF3
D2
SRF2
D1
SRF1
D0
SRF0
Default
0xBB80
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.
Table 33.
Bit
SRF [15:0]
Mnemonic
Sample Rate
Function
The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to
VRA, the sample rate is reset to 48 kHz.
PCM ADC RATE REGISTER
Index 0x32
Reg
No.
0x32
Name
PCM L/R
ADC
Rate
D15
SRA15
D14
SRA14
D13
SRA13
D12
SRA12
D11
SRA11
D10
SRA10
D9
SRA9
D8
SRA8
D7
SRA7
D6
SRA6
D5
SRA5
D4
SRA4
D3
SRA3
D2
SRA2
D1
SRA1
D0
SRA0
Default
0xBB80
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.
Table 34.
Bit
SRA [15:0]
Mnemonic
Sample Rate
Function
The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to
VRA, the sample rate is reset to 48 kHz.
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