ADSP-21363 Datasheet, PDF (25/44 Pages) Analog Devices – SHARC Processor

Preliminary Technical Data
ADSP-21363
Table 21. 16-bit Memory Read Cycle
Parameter
Min
Timing Requirements
t_DRS
Address/Data 15–0 Setup Before RD High
3.3
t_DRH
Address/Data 15–0 Hold After RD High
0
Switching Characteristics
t_ALEW
t_ADAS¹
ALE Pulse Width
Address/Data 15–0 Setup Before ALE Deasserted
2 × t_PCLK – 2
t_PCLK – 2.5
t_ALERW
ALE Deasserted to Read Asserted
2 × t_PCLK – 2
t_RRH
Delay Between RD Rising Edge to Next Falling Edge.
H + t_PCLK – 1
t_RWALE
Read Deasserted to ALE Asserted
F + H + 0.5
t_RDDRV
t_ADAH¹
t_ALEHZ¹
RD Address Drive After Read High
Address/Data 15–0 Hold After ALE Deasserted
ALE Deasserted to Address/Data15–0 in High Z
F + H + t_PCLK – 1
t_PCLK – 0.8
t_PCLK – 0.8
t_RW
RD Pulse Width
D–2
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t_PCLK
H = t_PCLK (if a hold cycle is specified, else H = 0)
F = 7 x t_PCLK (if FLASH_MODE is set else F = 0)
1 _{On reset, ALE is an active high cycle. However, it can be configured by software to be active low.}
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE
RD
WR
AD15-0
t_ALEW
t_ALERW
t_ADAS
t_ALEHZ
t_ADAH
VALID ADDRESS
t_RW
t_RWALE
t_{R R H}
t_RDDRV
t_DRS
t_{D R H}
VALID DATA
VALID
ADDRESS
Figure 18. Read Cycle For 16-Bit Memory Timing
Rev. PrA | Page 25 of 44 | September 2004