ADSP-21061LKSZ-160 Datasheet, PDF (25/52 Pages) Analog Devices – Commercial Grade SHARC DSP Microcomputer

ADSP-21061/ADSP-21061L
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is the
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Table 13. Memory Write—Bus Master
5 V and 3.3 V
Parameter
Min
Max
Unit
Timing Requirements
t_DAAK ACK Delay from Address, Selects^{1, 2}
t_DSAK
ACK Delay from WR Low¹
15 + 7DT/8 + W
ns
8 + DT/2 + W
ns
Switching Characteristics
t_DAWH Address, Selects to WR Deasserted²
17 + 15DT/16 + W
ns
t_DAWL Address, Selects to WR Low²
3 + 3DT/8
ns
t_WW
WR Pulse Width
13 + 9DT/16 + W
ns
t_DDWH Data Setup Before WR High
7 + DT/2 + W
ns
t_DWHA Address Hold After WR Deasserted
1 + DT/16 + H
ns
t_DATRWH Data Disable After WR Deasserted³
1 + DT/16 +H
6 + DT/16+H
ns
t_WWR WR High to WR, RD, DMAGx Low
8 + 7DT/16 + H
ns
t_DDWR Data Disable Before WR or RD Low
5 + 3DT/8 + I
ns
t_WDE
WR Low to Data Enabled
t_SADADC Address, Selects to ADRCLK High²
–1 + DT/16
ns
0 + DT/4
ns
W = (number of wait states specified in WAIT register) × t_CK.
H = t_CK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = t_CK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1 _{ACK delay/setup: User must meet tDAAK or tDSAK or synchronous specification tSAKC for deassertion of ACK (low), all three specifications must be met for assertion of ACK}
(high).
2 _{The falling edge of MSx, SW, BMS is referenced.}
3 _{For more information, see Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.}
ADDRESS
MSX, SW
BMS
WR
DATA
ACK
RD, DMAG
ADRCLK
(OUT)
t_DAWL
t_DAWH
t_WW
t_WDE
t_DAAK
t_DSAK
t_DDWH
t_DWHA
t_WWR
t_DATRWH
t_DDWR
t_SADADC
Figure 15. Memory Write—Bus Master
Rev. D | Page 25 of 52 | May 2013