ADSP-21061LKSZ-160 Datasheet, PDF (23/52 Pages) Analog Devices – Commercial Grade SHARC DSP Microcomputer

ADSP-21061/ADSP-21061L
Flags
Table 11. Flags
5 V and 3.3 V
Parameter
Min
Max
Timing Requirements
t_SFI
FLAG3–0 IN Setup Before CLKIN High¹
t_HFI
t_DWRFI
FLAG3–0 IN Hold After CLKIN High¹
FLAG3–0 IN Delay After RD/WR Low¹
t_HFIWR
FLAG3–0 IN Hold After RD/WR Deasserted¹
8 + 5DT/16
0 – 5DT/16
0
5 + 7DT/16
Switching Characteristics
t_DFO
t_HFO
t_DFOE
t_DFOD
FLAG3–0 OUT Delay After CLKIN High
FLAG3–0 OUT Hold After CLKIN High
CLKIN High to FLAG3–0 OUT Enable
CLKIN High to FLAG3–0 OUT Disable
16
4
3
14
1 _{Flag inputs meeting these setup and hold times for Instruction Cycle N will affect conditional instructions in Instruction Cycle N+2.}
Unit
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN
FLAG3–0 _OUT
CLKIN
FLAG3–0 _IN
RD WR
t_DFOE
t_SFI
t_DWRFI
FLAG INPUT
t_DFO
t_HFO
t_DFO
FLAG OUTPUT
t_HFI
t_HFIWR
Figure 13. Flags
t_DFOD
Rev. D | Page 23 of 52 | May 2013