AD9857 Datasheet, PDF (25/31 Pages) Analog Devices – CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter

SYSCLK/N
SYSCLK/2N
SYSCLK/4N
AD9857
PDCLK
TxENABLE
D<13:0>
SIGNAL PATH I
SIGNAL PATH Q
INVCIC CLOCK
DON'T CARE
I₀
Q₀
I₁
Q₁
I₂
I₀
Q₀
LATENCY THROUGH DATA ASSEMBLER LOGIC
IS 3 PDCLK CYCLES
INVERSE CIC
FILTER SETUP
TIME
Figure 31. Latency from D<13:0> to Signal Processing Chain, Four PDCLK Cycles
Q₂
I₁
Q₁
SYSCLK/N
SYSCLK/2N
SYSCLK/4N
PDCLK
TxENABLE
D<13:0> ^{DON'T CARE}
I₀
Q₀
I₁
Q₁
I₂
Q₂
I₃
Q₃
SIGNAL PATH I
I₀
I₁
SIGNAL PATH Q
Q₀
Q₁
INVCIC CLOCK
LATENCY THROUGH DATA ASSEMBLER LOGIC
IS 3 PDCLK CYCLES
INVERSE CIC FILTER SETUP TIME
Figure 32. Latency from D<13:0> to Signal Processing Chain, Five PDCLK Cycles
REV. 0
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