AD9857 Datasheet, PDF (24/31 Pages) Analog Devices – CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter

AD9857
Latency
The latency through the AD9857 is easiest to describe in terms
of System Clock (SYSCLK) cycles. Latency is a function of the
AD9857 configuration (that is, which mode and which optional
features are engaged). The latency is primarily affected by the
programmable interpolator’s rate.
The following values should be considered estimates because
observed latency may be data-dependent. The latency was cal-
culated using the linear delay model for FIR filters.
SYSCLK = REFCLK × Reference Clock Multiplier Factor
(1 If Bypassed, 4–20)
N = Programmable Interpolate Rate
(1 If Bypassed, 2–63)
Stage
Input Demux
Inverse CIC
Fixed Interpolator
Programmable
Interpolator
Quadrature
Modulator
Inverse SINC
Output Scaler
Table V.
Modulator
Mode
4×N
12 × N (Optional)
82 × N
Interpolator
Mode
8×N
12 × N (Optional)
82 × N
5×N+9
5×N+9
7
7 (Optional)
6 (Optional)
Not Used
7 (Optional)
6 (Optional)
Example
Interpolate Mode
Clock Multiplier = 4
Inverse CIC = On
Interpolate Rate = 20
Inverse SINC = Off
Output Scale = On
Latency = 8 × 20 + 12 × 20 + 82 × 20 + (5 × 20 + 9) + 6 = 2155
System Clocks/4 = 538.75 Reference Clock Periods
Latency for the Single-Tone Mode
In Single-Tone Mode, frequency hopping is accomplished by
alternately selecting the two profile input pins. The time required
to switch from one frequency to another is less than 30 System
Clock cycles (SYSCLK) with the Inverse SINC Filter and the
Output scaler engaged. With the Inverse SINC Filter disengaged,
the latency drops to less than 24 SYSCLK cycles.
Other Factors Affecting Latency
Another factor affecting latency is the internal clock phase rela-
tionship at the start of any burst transmission. For systems that
need to maintain exact SYSCLK cycle latency for all bursts, the
user must be aware of the possible difference in SYSCLK cycle
latency through the DEMUX, which precedes the signal process-
ing chain. The timing diagrams of Figures 31 and 32 describe
how the latency differs depending upon the phase relationship
between the PDCLK and the clock that samples data at the out-
put of the data assembler logic (labeled DEMUX on the block
diagram).
Regarding Figures 31 and 32, the SYSCLK/N trace represents
the clock frequency that is divided down from SYSCLK by the
CIC interpolation rate. That is, with SYSCLK equal 200 MHz
and the CIC interpolation rate equal 2 (N = 2), then SYSCLK/
N equals 100 MHz. The SYSCLK/2N and SYSCLK/4N signals
are divide by 2 and 4 of SYSCLK/N, respectively. For Quadra-
ture Modulation Mode the PDCLK is the SYSCLK/2N frequency
and the clock that samples data into the signal processing chain
is the SYSCLK/4N frequency. Note that SYSCLK/2N rising edges
create the transition of the SYSCLK/4N signal.
Figure 31 shows the timing for a burst transmission that starts
when the PDCLK (SYSCLK/2N) signal generates a rising edge
on the SYSCLK/4N clock. The latency from the D<13:0> pins
to the output of the data assembler logic is three PDCLK cycles.
The output is valid on the falling edge of SYSCLK/4N clock and is
sampled into the signal processing chain on the next rising edge
of the SYSCLK/4N clock (1/2 SYSCLK/4N clock cycle latency).
Figure 32 shows the timing for a burst transmission that starts
when the PDCLK (SYSCLK/2N) signal generates a falling edge
on the SYSCLK/4N clock. The latency from the D<13:0> pins
to the output of the data assembler logic is three PDCLK cycles.
This is identical to Figure 31, but note that output is valid on the
rising edge of SYSCLK/4N clock and is sampled into the signal
processing chain on the next rising edge of the SYSCLK/4N clock
(1 full SYSCLK/4N clock cycle latency).
The difference in latency (as related to SYSCLK clock cycles) is
SYSCLK/2N, or one PDCLK cycle.
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