AD9139 Datasheet, PDF (25/56 Pages) Analog Devices – 16-Bit, 1600 MSPS, TxDAC+ Digital-to- Analog Converter

Data Sheet
RESETTING THE FIFO
Upon device power-on, the read and write pointers start to roll
around the FIFO from an arbitrary slot; consequently, the FIFO
depth is unknown. To avoid a concurrent read and write to the
same FIFO address and to assure a fixed pipeline delay from
power-on to power-on, it is important to reset the FIFO pointers to
a known state each time the device powers on or wakes up. This
state is specified in the requested FIFO level (FIFO depth and
FIFO level are used interchangeably in this data sheet), which
consists of two parts: the integer FIFO level and the fractional
FIFO level.
The integer FIFO level represents the difference of the states
between the read and write points in the unit of input data period
(1/fDATA). The fractional FIFO level represents the difference of
the FIFO pointers that is smaller than the input data period.
The resolution of the fractional FIFO level is the input data period
divided by the interpolation ratio and, thus, it is equal to one
DACCLK cycle.
The exact FIFO level, that is, the FIFO latency, can be calculated
by
FIFO Latency = Integer Level + Fractional Level
Because the FIFO has eight data slots, there are eight possible
FIFO integer levels. The maximum supported interpolation rate
in the AD9139 is 2× interpolation. Therefore, there are two
possible FIFO fractional levels.
Two 3-bit registers in Register 0x23 are assigned to represent
the two FIFO levels, as follows:
• Bits[6:4] represent the FIFO integer level
• Bits[2:0] represent the FIFO fractional level
For example, if the interpolation rate is 2× and the desired total
FIFO depth is 4.5 input data periods, set the FIFO_LEVEL_
CONFIG (Register 0x23) to 0x41 (4 means four data cycles and
1 means one DAC cycle, which is half of a data cycle, in this
case).
Reset the FIFO and initialize the FIFO level using either of the
following methods:
• Serial port (SPI) initiated FIFO reset
• Frame initiated FIFO reset
AD9139
SERIAL PORT INITIATED FIFO RESET
A SPI initiated FIFO reset is the most common method to reset
the FIFO. To initialize the FIFO level through the serial port,
toggle FIFO_SPI_RESET_REQUEST (Register 0x25, Bit 0)
from 0 to 1 and back to 0. When the write to this register is
complete, the FIFO level is initialized to the requested FIFO level
and the readback of FIFO_SPI_RESET_ACK (Register 0x25, Bit 1)
is set to 1. The FIFO level readback, in the same format as the
FIFO level request, must be within ±1 DACCLK cycle of the
requested level. For example, if the requested value is 0x40 in
2× interpolation, the readback value should be one of the
following: 0x31, 0x40, or 0x41. The range of ±1 DACCLK cycle
indicates the default DAC latency uncertainty from power-on
to power-on without turning on synchronization.
The recommended procedure for a serial port FIFO reset is as
follows:
1. Configure the DAC in the desired interpolation mode
(Register 0x28[7]).
2. Ensure that the DACCLK and DCI clocks are running and
stable at the clock inputs.
3. Program Register 0x23 to 0x41.
4. Request the FIFO level reset by setting Register 0x25[0] to 1.
5. Verify that the device acknowledges the request by setting
Register 0x25[1] to 1.
6. Remove the request by setting Register 0x25[0] to 0.
7. Verify that the device drops the acknowledge signal by
setting Register 0x25[1] to 0.
8. Read back Register 0x06[2] and Register 0x06[1]. If both
bits are 0, continue to Step 9. If any of the two bits is 1,
program Register 0x23 to 0x40.
9. Read back Register 0x24 multiple times to verify that the
actual FIFO level is set to the requested level (Register 0x23),
and that the readback values are stable. By design, the
readback is within ±1 DACCLK around the requested
level.
FRAME INITIATED FIFO RESET
The frame input has two functions. One function is to indicate
the beginning of a byte stream in the byte interface mode, as
described in the Data Interface section. The other function is
to initialize the FIFO level by asserting the frame signal high
for at least the time interval required to load two samples of
data to the DAC. This corresponds to one DCI period in word
mode and two DCI periods in byte mode. Note that this
requirement of the frame pulse length is longer than that of the
frame signal when it serves only to assemble the byte stream.
The device accepts either a continuous frame or a one shot
frame signal.
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