AD9139 Datasheet, PDF (1/56 Pages) Analog Devices – 16-Bit, 1600 MSPS, TxDAC+ Digital-to- Analog Converter

Data Sheet
16-Bit, 1600 MSPS, TxDAC+ Digital-to-
Analog Converter
AD9139
FEATURES
GENERAL DESCRIPTION
Selectable 1× or 2× interpolation filter
Support input signal bandwidth up to 575 MHz
Very small inherent latency variation: <2 DAC clock cycles
Proprietary low spurious and distortion design
6-carrier GSM ACLR = 79 dBc at 200 MHz IF
SFDR >85 dBc (bandwidth = 300 MHz) at zero IF
Flexible 16-bit LVDS interface
Supports word and byte load
Multiple chip synchronization
Fixed latency and data generator latency compensation
FIFO eases system timing and includes error detection
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 700 mW at 1230 MSPS
72-lead LFCSP
APPLICATIONS
Wireless communications: 3G/4G and MC-GSM base stations,
wideband repeaters, software defined radios
Wideband communications: point-to-point, LMDS/MMDS
Transmit diversity/MIMO
Instrumentation
Automated test equipment
The AD9139 is an 16-bit, high dynamic range digital-to-analog
converter (DAC) that provides a sample rate of 1600 MSPS,
permitting a multicarrier generation up to the Nyquist frequency.
The AD9139 TxDAC+® includes features optimized for wideband
communication applications, including 1× and 2× interpolation, a
delay locked loop (DLL) powered high speed interface, sample
error detection, and parity detection. A 3-wire serial port
interface provides for the programming/readback of many
internal parameters. A full-scale output current can be
programmed over a range of 9 mA up to 33 mA. The AD9139 is
available in a 72-lead LFCSP.
PRODUCT HIGHLIGHTS
1. 575 MHz achievable input signal bandwidth.
2. Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
3. Very small inherent latency variation simplifies both software
and hardware design in the system. It allows easy multichip
synchronization for most applications.
4. Low power architecture improves power efficiency.
FUNCTIONAL BLOCK DIAGRAM
DCIP/DCIN
D15P/D15N
D0P/D0N
FRAMEP/PARITYP
FRAMEN/PARITYN
DLL
13-TAP
AD9139
HB1
2×
16
DAC 1
16-BIT
DAC_CLK
DACOUTP
DACOUTN
INTERNAL CLOCK TIMING AND CONTROL LOGIC
REF
10
AND
BIAS
VREF
FSADJ
PROGRAMMING
REGISTERS
SERIAL
INPUT/OUTPUT
PORT
POWER-ON
MULTICHIP
RESET SYNCHRONIZATION _{DAC_CLK}
SYNC
CLOCK
MULTIPLIER
CLK
RCVR
REF
RCVR
DACCLKP
DACCLKN
REFP/SYNCP
REFN/SYNCN
Figure 1.
Rev. 0
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