AD7856 Datasheet, PDF (25/32 Pages) Analog Devices – 5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC

Mode 2 (3-Wire SPI/QSPI Interface Mode)
This is the DEFAULT INTERFACE MODE.
In Figure 33 below we have the timing diagram for interface
Mode 2, which is the SPI/QSPI interface mode. Here the SYNC
input is active low and may be pulsed or permanently tied low.
If SYNC is permanently low, 16 clock pulses must be applied to
the SCLK pin for the part to operate correctly otherwise, with a
pulsed SYNC input, a continuous SCLK may be applied pro-
vided SYNC is low for only 16 SCLK cycles. In Figure 33 the
AD7856
SYNC going low disables the three-state on the DOUT pin. The
first falling edge of the SCLK after the SYNC going low clocks
out the first leading zero on the DOUT pin. The DOUT pin is
three-stated again a time, t₁₂, after the SYNC goes high. With
the DIN pin the data input has to be set up a time, t₇, before the
SCLK rising edge as the part samples the input data on the
SCLK rising edge in this case. If resetting the interface is re-
quired, the SYNC must be taken high and then low.
POLARITY PIN LOGIC HIGH
t₃ = –0.4t_SCLK MIN (NONCONTINUOUS SCLK) –/+0.4t_SCLK ns MIN/MAX (CONTINUOUS SCLK),
t₆ = 45/75ns MAX (A/K), t₇ = 30/40ns MIN (A/K), t₈ = 20ns MIN,
t₁₁ = 30ns MIN (NONCONTINUOUS SCLK), 30/0.4t_SCLK ns MIN/MAX (CONTINUOUS SCLK)
SYNC (I/P)
SCLK (I/P)
t₅
THREE-
DOUT (O/P) ^STATE
t₃
1
t₉
2
t₆
DB15
DB14
3
t₁₀
DB13
4
5
t₆
DB12
DB11
6
DB10
t₁₁
16
DB0
t₁₂
THREE-
STATE
DIN (I/P)
t₇
DB15
t₈
DB14
DB13 DB12
DB11
t₈
DB10
DB0
Figure 33. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input
DOUT Output and SYNC Input
REV. A
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