ADAU1961 Datasheet, PDF (23/76 Pages) Analog Devices – Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL

Data Sheet
Case 2: PLL Is Used
The core clock to the entire chip is off during the PLL lock
acquisition period. The user can poll the lock bit to determine
when the PLL has locked. After lock is acquired, the ADAU1961
can be started by asserting the core clock enable bit (COREN)
in Register R0 (clock control register, Address 0x4000). This bit
enables the core clock to all the internal blocks of the ADAU1961.
PLL Lock Acquisition
During the lock acquisition period, only Register R0 (Address
0x4000) and Register R1 (Address 0x4002) are accessible
through the control port. Because all other registers require a
valid master clock for reading and writing, do not attempt to
access any other register. Any read or write is prohibited until
the core clock enable bit (COREN) and the lock bit are both
asserted.
ADAU1961
To program the PLL during initialization or reconfiguration of
the clock setting, the following procedure must be followed:
1. Power down the PLL.
2. Reset the PLL control register.
3. Start the PLL.
4. Poll the lock bit.
5. Assert the core clock enable bit after the PLL lock
is acquired.
The PLL control register (Register R1, Address 0x4002) is a
48-bit register where all bits must be written with a single
continuous write to the control port.
Rev. A | Page 23 of 76