ADAU1961 Datasheet, PDF (1/76 Pages) Analog Devices – Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL

Data Sheet
Stereo, Low Power, 96 kHz, 24-Bit
Audio Codec with Integrated PLL
ADAU1961
FEATURES
GENERAL DESCRIPTION
24-bit stereo audio ADC and DAC: >98 dB SNR
Sampling rates from 8 kHz to 96 kHz
Low power: 17 mW record, 18 mW playback, 48 kHz
6 analog input pins, configurable for single-ended or
differential inputs
Flexible analog input/output mixers
Stereo digital microphone input
Analog outputs: 2 differential stereo, 2 single-ended stereo,
1 mono headphone output driver
PLL supporting input clocks from 8 MHz to 27 MHz
Analog automatic level control (ALC)
Microphone bias reference voltage
Analog and digital I/O: 3.3 V
I²C and SPI control interfaces
Digital audio serial data I/O: stereo and time-division
multiplexing (TDM) modes
Software-controllable clickless mute
32-lead, 5 mm × 5 mm LFCSP
−40°C to +105°C operating temperature range
Qualified for automotive applications
APPLICATIONS
The ADAU1961 is a low power, stereo audio codec that supports
stereo 48 kHz record and playback at 35 mW from a 3.3 V analog
supply. The stereo audio ADCs and DACs support sample rates
from 8 kHz to 96 kHz as well as a digital volume control.
The record path includes an integrated microphone bias circuit
and six inputs. The inputs can be mixed and muxed before the
ADC, or they can be configured to bypass the ADC. The
ADAU1961 includes a stereo digital microphone input.
The ADAU1961 includes five high power output drivers (two
differential and three single-ended), supporting stereo head-
phones, an earpiece, or other output transducer. AC-coupled
or capless configurations are supported. Individual fine level
controls are supported on all analog outputs. The output mixer
stage allows for flexible routing of audio.
The serial control bus supports the I²C and SPI protocols. The
serial audio bus is programmable for I²S, left-/right-justified,
and TDM modes. A programmable PLL supports flexible clock
generation for all standard integer rates and fractional master
clocks from 8 MHz to 27 MHz.
Automotive head units
Automotive amplifiers
Navigation systems
Rear-seat entertainment systems
FUNCTIONAL BLOCK DIAGRAM
JACKDET/MICIN
HP JACK _REGULATOR
DETECTION
ADAU1961
LAUX
LINP
LINN
RINP
RINN
RAUX
INPUT
MIXERS
ALC
ADC
ADC
ADC
DAC
DIGITAL DIGITAL
FILTERS FILTERS
DAC
DAC
OUTPUT
MIXERS
LOUTP
LOUTN
LHP
MONOOUT
RHP
ROUTP
ROUTN
MICBIAS
MICROPHONE
BIAS
PLL
SERIAL DATA
INPUT/OUTPUT PORTS
I²C/SPI
CONTROL PORT
MCLK ADC_SDATA
DAC_SDATA ADDR0/ ADDR1/ SCL/ SDA/
CLATCH CDATA CCLK COUT
Figure 1.
Rev. A
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