AD9957 Datasheet, PDF (23/38 Pages) Analog Devices – 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC

PRELIMINARY TECHNICAL DATA
eration is complete. All data written to (read from) the AD9957/10
must be (will be) in MSB first order. If the LSB mode is active, the
serial port controller will generate the least significant byte address
first followed by the next greater significant byte addresses until the
IO operation is complete. All data written to (read from) the
AD9957/10 must be (will be) in LSB first order.
RAM IO VIA SERIAL PORT
Accessing the RAM via the serial port is identical to any other se-
rial IO operation except that the number of bytes transferred is
determined by the address space between the beginning address
and the final address as specified in the current RAM Segment
Control Word (RSCW). The final address describes the most sig-
nificant word address for all IO transfers and the beginning address
specifies the least significant address.
RAM IO supports MSB/LSB first operation. When in MSB first
mode, the first data byte will be for the most significant byte of the
memory address described by the final address with the remaining
three bytes making up the lesser significant bytes of that address.
The remaining bytes come in most significant to least significant,
destined for RAM addresses generated in descending order until
the final four bytes are written into the address specified as the
beginning address. When in LSB first mode, the first data byte will
be for the least significant byte of the memory (specified by the
beginning address) with the remaining three bytes making up the
greater significant bytes of that address. The remaining bytes come
in least significant to most significant, destined for RAM addresses
generated in ascending order until the final four bytes are written
into the memory address described by the final address. Of course,
the bit order for all bytes is least significant to most significant first
when in the LSB first bit is set. When the LSB first bit is cleared
(default) the bit order for all bytes is most significant to least sig-
nificant.
RAM CONTROL MODES
BASEBAND INPUT SCALING WITH RAM
In QDUC and DAC interpolation modes, the baseband data may
be scaled via the 18x16 bit multiplier(s)(IS,QS), whose multiplicand
is driven by the RAM. This function offers the customer a means
of performing an arbitrary amplitude ramp up/down of the base-
band data. The ramp profile is generated at the input sample rate
and interpolated up to the DAC sample rate through the baseband
signal chain in the same manner as the I/Q data, significantly re-
ducing power dissipation.
In this configuration, the 32-bit RAM words are partitioned into
two 16-bit words. The data being used as a scale factor for the I/Q
words supplied by the user to the 18-bit parallel port. The RAM
words are accessed at the IQ sample rate (output rate of the data
assembler logic).
The scale factor, driven from the RAM, is an unsigned value. All
zeros multiplies the baseband data by 0 (decimal) and FFFFh mul-
AD9957
tiplies the baseband data by nearly 1.0 (0.FFFF equates to .99985).
Invoke the input Data Scaling Mode using the RAM enable bit and
the RAM QDUC Evaluation bit, while in QDUC or interpolating
DAC mode. The Input Scale Factor Control (ISFC) pin is used to
start and stop the RAM controller. Two 48-bit registers are dedi-
cated for controlling the RAM segmentation and ramp rates. See
the QDUC RAM Segment #0 (QRSR0) and the QDUC RAM Seg-
ment #1 (QRSR1) registers in the register map.
I AND Q INPUT DATA FROM RAM
In the QDUC mode, the RAM can be configured to supply IQ data.
The RAM is partitioned as two 16-bit words. The two words are
routed to the baseband data pathway.
One word is routed to the "I" channel and the other word is
routed to the "Q" channel. This will allow the user to easily
generate a customized modulation waveform composed of up
to 1024 I/Q samples without the need for external support cir-
cuitry to supply data to the parallel input port. This feature is
an attempt to simplify the user’s design/debug process when the
device is incorporated into a new product design.
Synchronizing Multiple AD9957s Devices
The AD9957 product includes circuitry that enables multiple
AD9957 products to be automatically synchronized to one an-
other. Multiple devices are considered synchronized when the
state of the clock generation state machines are identical for all
parts. Multiple part synchronization can be achieved by a sim-
ple connection of LVDS outputs on the master device to the
LVDS inputs of the slave device(s). Devices are configured as
master and slaves through programming bits, accessible via the
serial port.
Pipeline Matching of the FTW, Phase Offset,
and Output Scaling
The AD9957 offers a feature that enables the simultaneous applica-
tion of changes in frequency, phase and amplitude to be applied in
a manner that allows these parameters to be synchronized to the
specific pipe delays of the preceding logic blocks. This feature is
controllable via the serial port and is activated by writing the Match
Pipe Delays Active bit to a logic one.
Output Shaped On-Off Keying modes
Auto and Manual shaped On-Off keying modes are supported.
AUTO mode generates a linear scale factor at a rate determined by
the Amplitude Ramp Rate Register (ARR), controlled by an exter-
nal pin (OSK). MANUAL mode allows the user to directly control
the output amplitude by writing the scale factor value into the Am-
plitude Scale Factor Register (ASFR).
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