AD9957 Datasheet, PDF (1/38 Pages) Analog Devices – 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC

1 GSPS Quadrature Digital Upconverter
w/18-Bit IQ Data Path and 14-Bit DAC
PRELIMINARY TECHNICAL DATA
FEATURES
1GSPS internal clock speed (up to 400MHz analog out)
Integrated 1GSPS 14-bit DAC
250 MHz I/Q data throughput rate
Phase noise ≤ –123 dBc/Hz (400 MHz carrier)
Excellent dynamic performance >80 dB narrowband SFDR
8 Programmable Profiles for shift keying
SIN(X)/(X) Correction (Inverse SINC filter)
Reference Clock Multiplier
Internal oscillator for a single crystal operation
Software and hardware controlled power-down
Integrated RAM
Phase modulation capability
Multichip synchronization
Easy interface to Blackfin™ SPORT
Interpolation factors from 4x to 252x
Test tone circuitry
Interpolation DAC Mode
Gain control DAC
Internal divider allows references up to 2 GHz
1.8V & 3.3V Power Supplies
100 Lead TQFP package
APPLICATIONS
HFC Data, Telephony & Video Modems
Wireless Base Station Transmission
Broadband Communications Transmissions
Internet Telephony
AD9957
GENERAL DESCRIPTION
The AD9957 functions as a universal I/Q modulator and agile
upconverter for communications systems where cost, size,
power consumption and dynamic performance are critical. The
AD9957 integrates a high speed Direct Digital Synthesizer
(DDS), a high performance, high speed 14-bit digital to analog
converter (DAC), clock multiplier circuitry, digital filters and
other DSP functions onto a single chip. It provides for base
band up-conversion for data transmission in a wired or wireless
communications system.
The AD9957 is the third offering in a family of a quadrature
digital upconverters (QDUCs), which includes the AD9857 and
AD9856. It offers performance gains in operating speed, power
consumption and spectral performance. Unlike its predeces-
sors, it also supports a 16-bit serial input mode for I/Q base
band data. The device can alternatively be programmed to op-
erate as a single-tone sinusoidal source or as an interpolating
DAC.
The Reference Clock input circuitry includes a crystal oscillator,
a high speed divide-by-two input, and a low noise PLL for mul-
tiplication of the reference clock frequency.
The user interface to the control functions includes a serial port
easily configured to interface to the SPORT of the Blackfin DSP
and profile pins which enable fast and easy shift keying of any
signal parameter (phase, frequency, and amplitude).
Figure 1: Basic Block Diagram
Rev. PrF
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