AD9847AKSTZ Datasheet, PDF (23/28 Pages) Analog Devices – 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver

AD9847
FLD
ODD FIELD
VD
EVEN FIELD
HD
PxGA GAIN
REGISTER ^{X X}
01
2
0
2
1
02
0
1
2
0
01 2 0 21 0 20 1 2 0
0
NOTES
1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “012012” LINE.
2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER, STEERING BETWEEN “012012” AND “210210” LINES.
3. FLD STATUS IS IGNORED.
Figure 16e. Three-Color Mode II
FLD
ODD FIELD
EVEN FIELD
VD
HD
PxGA GAIN
REGISTER
X
X
01
23
0
1 23
0
1
2
3
01 2 3 01 2 30 1 2 3
0
NOTES
1. EACH LINE FOLLOWS “01230123” STEERING PATTERN.
2. VD AND HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO GAIN REGISTER “0.”
3. FLD STATUS IS IGNORED.
Figure 16f. Four-Color Mode
FLD
ODD FIELD
EVEN FIELD
VD
HD
PxGA GAIN
REGISTER
X
X
01
23
2
3 01
0
1
2
3
01 2 3 23 0 10 1 2 3
0
NOTES
1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “01230123” LINE.
2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “01230123” AND “23012301” LINES.
3. FLD STATUS IS IGNORED.
Figure 16g. Four-Color Mode II
REV. A
–23–