AD9847AKSTZ Datasheet, PDF (14/28 Pages) Analog Devices – 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver

AD9847
Bit
Address Content Width
PBLK # Bits 146
C5
[0]
1
C6
[0]
1
C7
[0]
1
C8
[5:0]
6
C9
[5:0]
6
CA
[5:0]
6
CB
[5:0]
6
CC
[0]
1
CD
[5:0]
6
CE
[5:0]
6
CF
[5:0]
6
D0
[5:0]
6
D1
[0]
1
D2
[5:0]
6
D3
[5:0]
6
D4
[5:0]
6
D5
[5:0]
6
D6
[0]
1
D7
[5:0]
6
D8
[5:0]
6
D9
[5:0]
6
DA
[5:0]
6
0
DB
[1:0]
2
DC
[5:0]
6
DD
[5:0]
6
DE
[1:0]
2
DF
[5:0]
6
E0
[5:0]
6
E1
[1:0]
2
E2
[5:0]
6
E3
[5:0]
6
E4
[1:0]
2
Default
Value Register Name
Register Description
01
pblkdir
PBLK Internal/External (0 = Internal, 1 = External)
00
pblkpol
PBLK External Active Polarity (0 = Low Active, 1 = High Active)
01
pblkspol0
Sequence #0: Start Polarity for PBLK
3D
pblktog1_0[5:0] Sequence #0: Toggle Position 1 for PBLK
00
pblktog1_0[11:6]
2A
pblkbtog2_0[5:0] Sequence #0: Toggle Position 2 for PBLK
06
pblkbtog2_0[11:6]
00
pblkspol1
Sequence #1: Start Polarity for PBLK
2A
pblktog1_1[5:0] Sequence #1: Toggle Position 1 for PBLK
06
pblktog1_1[11:6]
3F
pblktog2_1[5:0] Sequence #1: Toggle Position 2 for PBLK
3F
pblktog2_1[11:6]
00
pblkspol2
Sequence #2: Start Polarity for PBLK
3F
pblktog1_2[5:0] Sequence #2: Toggle Position 1 for PBLK
3F
pblktog1_2[11:6]
3F
pblktog2_2[5:0] Sequence #2: Toggle Position 2 for PBLK
3F
pblktog2_2[11:6]
01
pblkspol3
Sequence #3: Start Polarity for PBLK
3F
pblktog1_3[5:0] Sequence #3: Toggle Position 1 for PBLK
3F
pblktog1_3[11:6]
3F
pblktog2_3[5:0] Sequence #3: Toggle Position 2 for PBLK
3F
pblktog2_3[11:6]
00
pblkscp0
PBLK Sequence-Change-Position #0 (Hardcoded to 0)
02
pblksptr0
PBLK Sequence Pointer for SCP #0
01
pblkscp1[5:0]
PBLK Sequence-Change-Position #1
00
pblkscp1[11:6]
01
pblksptr1
PBLK Sequence Pointer for SCP #1
02
pblkscp2[5:0]
PBLK Sequence-Change-Position #2
00
pblkscp2[11:6]
00
pblksptr2
PBLK Sequence Pointer for SCP #2
37
pblkscp3[5:0]
PBLK Sequence-Change-Position #3
03
pblkscp3[11:6]
02
pblksptr3
PBLK Sequence Pointer for SCP #3
H1–H4, RG, SHP, SHD # Bits 53
E5
[0]
1
00
E6
[5:0]
6
00
E7
[5:0]
6
20
E8
[2:0]
3
03
E9
[2:0]
3
03
EA
[2:0]
3
03
EB
[2:0]
3
03
EC
[0]
1
00
ED
[5:0]
6
00
EE
[5:0]
6
10
EF
[2:0]
3
02
F0
[5:0]
6
24
F1
[5:0]
6
00
h1pol
h1posloc
h1negloc
h1drv
h2drv
h3drv
h4drv
rgpol
rgposloc
rgnegloc
rgdrv
shpposloc
shdposloc
H1/H2 Polarity Control (0 = No Inversion, 1 = Inversion)
H1 Positive Edge Location
H1 Negative Edge Location
H1 Drive Strength (0 = OFF, 1 = 3.5 mA, 2 = 7 mA,
3 = 10.5 mA, 4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA)
H2 Drive Strength
H3 Drive Strength
H4 Drive Strength
RG Polarity Control (0 = No Inversion, 1 = Inversion)
RG Positive Edge Location
RG Negative Edge Location
RG Drive Strength (0 = OFF, 1 = 3.5 mA, 2 = 7 mA,
3 = 10.5 mA, 4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA)
SHP (Positive) Edge Sampling Location
SHD (Positive) Edge Sampling Location
–14–
REV. A