AD9681_17 Datasheet, PDF (23/41 Pages) Analog Devices – 1.8 V Analog-to-Digital Converter

AD9681
If the internal reference of the AD9681 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 40 shows
how the internal reference voltage is affected by loading.
0
–0.5
–1.0
–1.5
INTERNAL V_REF = 1V
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (mA)
Figure 40. VREF Error vs. Load Current
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 41 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
4
2
0
–2
–4
–6
–8
–40
–15
10
35
60
85
TEMPERATURE (°C)
Figure 41. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 34). The internal buffer generates the
positive and negative full-scale references for the ADC core. There-
fore, limit the external reference to a maximum of 1.0 V.
Do not leave the SENSE pin floating.
Data Sheet
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9681 sample clock
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 28) and require no external bias.
Clock Input Options
The AD9681 has a flexible clock input structure. The clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless
of the type of signal being used, clock source jitter is of the utmost
concern, as described in the Jitter Considerations section.
Figure 42 and Figure 43 show two preferred methods for clocking
the AD9681 (at clock rates of up to 1 GHz prior to the internal
clock divider). A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF transformer
or an RF balun.
The RF balun configuration is recommended for clock frequencies
from 125 MHz to 1 GHz, and the RF transformer is recommended
for clock frequencies from 10 MHz to 200 MHz. The antiparallel
Schottky diodes across the transformer/balun secondary winding
limit clock excursions into the AD9681 to approximately 0.8 V p-p
differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9681 while
preserving the fast rise and fall times of the signal that are critical
to achieving a low jitter performance. However, the diode capaci-
tance comes into play at frequencies above 500 MHz. Take care
when choosing the appropriate signal limiting diode.
CLOCK
INPUT
0.1µF
Mini-Circuits^®
ADT1-1WT, 1:1 Z
XFMR ^0.1µF
50Ω ^100Ω
0.1µF
0.1µF
SCHOTTKY
DIODES:
HSMS2822
CLK+
ADC
CLK–
Figure 42. Transformer Coupled Differential Clock (Up to 200 MHz)
CLOCK
INPUT
0.1µF
50Ω
0.1µF
0.1µF
0.1µF
SCHOTTKY
DIODES:
HSMS2822
CLK+
ADC
CLK–
Figure 43. Balun Coupled Differential Clock (Up to 1 GHz)
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