AD9681_17 Datasheet, PDF (1/41 Pages) Analog Devices – 1.8 V Analog-to-Digital Converter

Data Sheet
Octal, 14-Bit, 125 MSPS, Serial LVDS,
1.8 V Analog-to-Digital Converter
AD9681
FEATURES
Low power
8 ADC channels integrated into 1 package
110 mW per channel at 125 MSPS with scalable power
options
SNR: 74 dBFS (to Nyquist); SFDR: 90 dBc (to Nyquist)
DNL: ±0.8 LSB (typical); INL: ±1.2 LSB (typical)
Crosstalk, worst adjacent channel, 70 MHz, −1 dBFS: −83 dB
typical
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Power-down and standby modes
APPLICATIONS
Medical imaging
Communications receivers
Multichannel data acquisition
GENERAL DESCRIPTION
The AD9681 is an octal, 14-bit, 125 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The device operates at a conversion rate of up to 125 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and an LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The AD9681 automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. Data clock outputs (DCO±1,
DCO±2) for capturing data on the output and frame clock outputs
(FCO±1, FCO±2) for signaling a new output byte are provided.
Individual channel power-down is supported, and the device
typically consumes less than 2 mW when all channels are disabled.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
AVDD PDWN DRVDD
AD9681
VIN+A1
VIN–A1
VIN+A2
VIN–A2
14
PIPELINE
ADC
14
PIPELINE
ADC
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
D0+A1
D0–A1
D1+A1
D1–A1
D0+A2
D0–A2
D1+A2
D1–A2
VIN+D1
VIN–D1
VIN+D2
VIN–D2
VREF
SENSE
VCM1, VCM2
GND
14
PIPELINE
ADC
14
PIPELINE
ADC
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
REF
1V
SELECT
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL PORT
INTERFACE
CLOCK
MANAGEMENT
D0+D1
D0–D1
D1+D1
D1–D1
D0+D2
D0–D2
D1+D2
D1–D2
FCO+1, FCO+2
FCO–1, FCO–2
DCO+1, DCO+2
DCO–1, DCO–2
Figure 1.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as programmable clock and data
alignment and programmable digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The AD9681 is available in an RoHS-compliant, 144-ball
CSP-BGA. It is specified over the industrial temperature range of
−40°C to +85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight ADCs are contained in a small,
10 mm × 10 mm package.
2. Low Power. The device dissipates 110 mW per channel at
125 MSPS with scalable power options.
3. Ease of Use. Data clock outputs (DCO±1, DCO±2) operate
at frequencies of up to 500 MHz and support double data
rate (DDR) operation.
4. User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
Rev. C
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