AD7172-2 Datasheet, PDF (23/61 Pages) Analog Devices – True rail-to-rail analog and reference input buffers

AD7172-2
8-BIT COMMAND
CS
8 BITS, 16 BITS,
OR 24 BITS OF DATA
DIN
CMD
DATA
SCLK
Figure 46. Writing to a Register
(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;
Data Length on DIN Is Dependent on the Register Selected)
8-BIT COMMAND
8 BITS, 16 BITS,
24 BITS, OR
32 BITS OUTPUT
CS
DIN
DOUT/RDY
CMD
DATA
SCLK
Figure 47. Reading from a Register
(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;
Data Length on DOUT/RDY Is Dependent on the Register Selected)
Reading the ID register is the recommended method for verifying
correct communication with the device. The ID register is a
read only register and contains the value 0x00DX for the
AD7172-2. The communications register and the ID register details
are described in Table 9 and Table 10.
AD7172-2 RESET
After a power-up cycle and when the power supplies are stable,
a device reset is required. In situations where interface synchro-
nization is lost, a device reset is also required. A write operation
of at least 64 serial clock cycles with DIN high returns the ADC to
the default state by resetting the entire device, including the register
contents. Alternatively, if CS is being used with the digital interface,
returning CS high sets the digital interface to the default state and
halts any serial interface operation.
Data Sheet
CONFIGURATION OVERVIEW
After power-on or reset, the AD7172-2 default configuration is
as follows:
• Channel configuration: CH0 is enabled, AIN0 is selected
as the positive input, and AIN1 is selected as the negative
input. Setup 0 is selected.
• Setup configuration: The internal reference and the analog
input buffers are disabled. The reference input buffers are
also disabled. An external reference on the REF± pins is
selected.
• Filter configuration: The sinc5 + sinc1 filter is selected and
the maximum output data rate of 31.25 kSPS is selected.
• ADC mode: Continuous conversion mode and the internal
oscillator are enabled.
• Interface mode: CRC and data + status output are disabled.
Note that only a few of the register setting options are shown;
this list is just an example. For full register information, see the
Register Details section.
Figure 48 shows an overview of the suggested flow for changing
the ADC configuration, divided into the following three blocks:
• Channel configuration (see Box A in Figure 48)
• Setup configuration (see Box B in Figure 48)
• ADC mode and interface mode configuration (see Box C
in Figure 48)
Channel Configuration
The AD7172-2 has four independent channels and four independ-
ent setups. The user can select any of the analog input pairs on
any channel, as well as any of the four setups for any channel,
giving the user full flexibility in the channel configuration. This
also allows per channel configuration when using differential
inputs and single-ended inputs because each channel can have a
dedicated setup.
Channel Registers
The channel registers select which of the five analog input pins
(AIN0 to AIN4) are used as either the positive analog input
(AIN+) or the negative analog input (AIN−) for that channel.
This register also contains a channel enable/disable bit and the
setup selection bits, which select which of the four available
setups to use for this channel.
When the AD7172-2 is operating with more than one channel
enabled, the channel sequencer cycles through the enabled
channels in sequential order, from Channel 0 to Channel 3. If a
channel is disabled, it is skipped by the sequencer. Details of the
channel register for Channel 0 are shown in Table 11.
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