AD7172-2 Datasheet, PDF (1/61 Pages) Analog Devices – True rail-to-rail analog and reference input buffers

Data Sheet
Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta
ADC with True Rail-to-Rail Buffers
AD7172-2
FEATURES
GENERAL DESCRIPTION
Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
Channel scan data rate of 6.21 kSPS/channel (161 µs settling)
Performance specifications
17.2 noise free bits at 31.25 kSPS
24 noise free bits at 5 SPS
INL: ±2 ppm of FSR
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
User configurable input channels
2 fully differential channels or 4 single-ended channels
Crosspoint multiplexer
On-chip 2.5 V reference (±2 ppm/°C drift)
True rail-to-rail analog and reference input buffers
Internal or external clock
Power supply
AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V
Split supply with AVDD1 and AVSS at ±2.5 V or ±1.65 V
ADC current: 1.5 mA
Temperature range: −40°C to +105°C
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
Serial port interface (SPI), QSPI-, MICROWIRE-, and DSP-
compatible
APPLICATIONS
Process control: PLC/DCS modules
Temperature and pressure measurement
Medical and scientific multichannel instrumentation
Chromatography
The AD7172-2 is an intelligent, low noise, low power, multiplexed,
Σ-Δ analog-to-digital converter (ADC) with 2- or 4-channel
(fully differential/single-ended) inputs for low bandwidth
signals. The AD7172-2 has a maximum channel scan rate of
6.21 kSPS (161 µs) for fully settled data. The output data rates
range from 1.25 SPS to 31.25 kSPS.
The AD7172-2 integrates key analog and digital signal condition-
ing blocks to allow users to configure an individual setup for each
analog input channel in use via the SPI. Integrated true rail-to-rail
buffers on the analog inputs and external reference inputs provide
easy to drive high impedance inputs. The precision 2.5 V low drift
(2 ppm/°C) band gap internal reference (with an output reference
buffer) adds embedded functionality to reduce the external
component count.
The digital filter allows simultaneous 50 Hz and 60 Hz rejection
at a 27.27 SPS output data rate. The user can switch between
different filter options according to the demands of each channel in
the application, with further digital processing functions such as
offset and gain calibration registers, which are also configurable on
a per channel basis. General-purpose inputs/outputs (GPIOs)
control external multiplexers synchronous to the ADC conversion
timing.
The specified operating temperature range is −40°C to +105°C.
The AD7172-2 is in a 24-lead TSSOP package.
Note that, throughout this data sheet, the dual function pin
names are referenced by the relevant function only.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 REGCAPA
REF– REF+ REFOUT
IOVDD REGCAPD
CROSSPOINT
MULTIPLEXER
1.8V
LDO
AIN0
AIN1
AIN2
AVDD
AVDD1
AVSS
RAIL-TO-RAIL
REFERENCE
INPUT BUFFERS
Σ-Δ ADC
BUFFERED
PRECISION
REFERENCE
INT
REF
DIGITAL
FILTER
1.8V
LDO
SERIAL
INTERFACE
AND CONTROL
AIN3
AIN4
RAIL-TO-RAIL
ANALOG INPUT
AVSS
BUFFERS
TEMPERATURE
SENSOR
GPIO AND
MUX
I/O CONTROL
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
AD7172-2
CS
SCLK
DIN
DOUT/RDY
SYNC/ERROR
AVSS
GPIO0 GPIO1
XTAL1 XTAL2/CLKIO
Figure 1.
DGND
Rev. A
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