ADSP-BF606 Datasheet, PDF (22/44 Pages) Analog Devices – Blackfin Dual Core

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Preliminary Technical Data
Table 7. Processor Multiplexing Scheme (Continued)
Signal Name
PD_08/UART0_RX/TM0_ACI0
PD_09/SPI0_SEL5/UART0_RTS/SPI1_SEL4
PD_10/SPI0_RDY/UART0_CTS/SPI1_SEL3
PD_11/SPI0_SEL1/SPI0_SS
PD_12/SPI1_SEL1/EPPI0_D20/SPT1_AD1/
SPI1_SS
PD_13/SPI1_MOSI/TM0_ACLK5
PD_14/SPI1_MISO/TM0_ACLK6
PD_15/SPI1_SEL2/EPPI0_D21/SPT1_AD0
Port E
PE_00/SPI1_D3/EPPI0_D18/SPT1_BD1
PE_01/SPI1_D2/EPPI0_D19/SPT1_BD0
PE_02/SPI1_RDY/EPPI0_D22/SPT1_ACLK
PE_03/EPPI0_D16/ACM0_FS/SPT1_BFS
PE_04/EPPI0_D17/ACM0_CLK/SPT1_BCLK
PE_05/EPPI0_D23/SPT1_AFS
PE_06/SPT1_ATDV/EPPI0_FS3/LP3_CLK
PE_07/SPT1_BTDV/EPPI0_FS2/LP3_ACK
PE_08/PWM0_SYNC/EPPI0_FS1/LP2_ACK/
ACM0_T0
PE_09/EPPI0_CLK/LP2_CLK/PWM0_TRIP0
PE_10/ETH1_MDC/PWM1_DL/RSI0_D6
PE_11/ETH1_MDIO/PWM1_DH/RSI0_D7
PE_12/ETH1_PHYINT/PWM1_CL/RSI0_D5
PE_13/ETH1_CRS/PWM1_CH/RSI0_D4
PE_14/ETH1_RXERR/SPT2_ATDV/TM0_TMR0
PE_15/ETH1_RXD1/PWM1_BL/RSI0_D3
Port F
PF_00/PWM0_AL/EPPI0_D00/LP2_D0
PF_01/PWM0_AH/EPPI0_D01/LP2_D1
PF_02/PWM0_BL/EPPI0_D02/LP2_D2
PF_03/PWM0_BH/EPPI0_D03/LP2_D3
PF_04/PWM0_CL/EPPI0_D04/LP2_D4
PF_05/PWM0_CH/EPPI0_D05/LP2_D5
PF_06/PWM0_DL/EPPI0_D06/LP2_D6
PF_07/PWM0_DH/EPPI0_D07/LP2_D7
PF_08/SPI1_SEL5/EPPI0_D08/LP3_D0
PF_09/SPI1_SEL6/EPPI0_D09/LP3_D1
PF_10/ACM0_A4/EPPI0_D10/LP3_D2
PF_11/EPPI0_D11/LP3_D3/PWM0_TRIP1
PF_12/ACM0_A2/EPPI0_D12/LP3_D4
PF_13/ACM0_A3/EPPI0_D13/LP3_D5
PF_14/ACM0_A0/EPPI0_D14/LP3_D6
PF_15/ACM0_A1/EPPI0_D15/LP3_D7
Port G
PG_00/ETH1_RXD0/PWM1_BH/RSI0_D2
PG_01/SPT2_AFS/TM0_TMR2/CAN0_TX
Function
PD Position 8/UART0 Receive/TIMER0 Alternate Capture Input 0
PD Position 9/SPI0 Slave Select Output 5/UART0 Request to Send/SPI1 Slave Select Output 4
PD Position 10/SPI0 Ready/UART0 Clear to Send/SPI1 Slave Select Output 3
PD Position 11/SPI0 Slave Select Output 1/SPI0 Slave Select Input
PD Position 12/SPI1 Slave Select Output 1/EPPI0 Data 20/SPORT1 Channel A Data 1/
SPI1 Slave Select Input
PD Position 13/SPI1 Master Out, Slave In/TIMER0 Alternate Clock 5
PD Position 14/SPI1 Master In, Slave Out/TIMER0 Alternate Clock 6
PD Position 15/SPI1 Slave Select Output 2/EPPI0 Data 21/SPORT1 Channel A Data 0
PE Position 0/SPI1 Data 3/EPPI0 Data 18/SPORT1 Channel B Data 1
PE Position 1/SPI1 Data 2/EPPI0 Data 19/SPORT1 Channel B Data 0
PE Position 2/SPI1 Ready/EPPI0 Data 22/SPORT1 Channel A Clock
PE Position 3/EPPI0 Data 16/ACM0 Frame Sync/SPORT1 Channel B Frame Sync
PE Position 4/EPPI0 Data 17/ACM0 Clock/SPORT1 Channel B Clock
PE Position 5/EPPI0 Data 23/SPORT1 Channel A Frame Sync
PE Position 6/SPORT1 Channel A Transmit Data Valid/EPPI0 Frame Sync 3 (FIELD)/LP3 Clock
PE Position 7/SPORT1 Channel B Transmit Data Valid/
EPPI0 Frame Sync 2 (VSYNC)/LP3 Acknowledge
PE Position 8/PWM0 Sync/EPPI0 Frame Sync 1 (HSYNC)/LP2 Acknowledge/
ACM0 External Trigger 0
PE Position 9/EPPI0 Clock/LP2 Clock/PWM0 Shutdown Input 0
PE Position 10/ETH1 Management Channel Clock/PWM1 Channel D Low Side/RSI0 Data 6
PE Position 11/ETH1 Management Channel Serial Data/PWM1 Channel D High Side/RSI0 Data 7
PE Position 12/ETH1 RMII Management Data Interrupt/PWM1 Channel C Low Side/RSI0 Data 5
PE Position 13/ETH1 Carrier Sense/RMII Receive Data Valid/PWM1 Channel C High Side/
RSI0 Data 4
PE Position 14/ETH1 Receive Error/SPORT2 Channel A Transmit Data Valid/ TIMER0 Timer 0
PE Position 15/ETH1 Receive Data 1/PWM1 Channel B Low Side/RSI0 Data 3
PF Position 0/PWM0 Channel A Low Side/EPPI0 Data 0/LP2 Data 0
PF Position 1/PWM0 Channel A High Side/EPPI0 Data 1/LP2 Data 1
PF Position 2/PWM0 Channel B Low Side/EPPI0 Data 2/LP2 Data 2
PF Position 3/PWM0 Channel B High Side/EPPI0 Data 3/LP2 Data 3
PF Position 4/PWM0 Channel C Low Side/EPPI0 Data 4/LP2 Data 4
PF Position 5/PWM0 Channel C High Side/EPPI0 Data 5/LP2 Data 5
PF Position 6/PWM0 Channel D Low Side/EPPI0 Data 6/LP2 Data 6
PF Position 7/PWM0 Channel D High Side/EPPI0 Data 7/LP2 Data 7
PF Position 8/SPI1 Slave Select Output 5/EPPI0 Data 8/LP3 Data 0
PF Position 9/SPI1 Slave Select Output 6/EPPI0 Data 9/LP3 Data 1
PF Position 10/ACM0 Address 4/EPPI0 Data 10/LP3 Data 2
PF Position 11/EPPI0 Data 11/LP3 Data 3/PWM0 Shutdown Input 1
PF Position 12/ACM0 Address 2/EPPI0 Data 12/ LP3 Data 4
PF Position 13/ACM0 Address 3/EPPI0 Data 13/ LP3 Data 5
PF Position 14/ACM0 Address 0/EPPI0 Data 14/ LP3 Data 6
PF Position 15/ACM0 Address 1/EPPI0 Data 15/ LP3 Data 7
PG Position 0/ETH1 Receive Data 0/PWM1 Channel B High Side/RSI0 Data 2
PG Position 1/SPORT2 Channel A Frame Sync/TIMER0 Timer 2/CAN0 Transmit
Rev. PrD | Page 22 of 44 | March 2012