ADSP-BF606 Datasheet, PDF (1/44 Pages) Analog Devices – Blackfin Dual Core

Blackfin Dual Core
Embedded Processor
Preliminary Technical Data ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
FEATURES
Dual-core symmetric high-performance Blackfin processor,
up to 500 MHz per core
Each core contains two 16-bit MACs, two 40-bit ALUs, and a
40-bit barrel shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Pipelined Vision Processor provides hardware to process sig-
nal and image algorithms used for pre- and co-processing
of video frames in ADAS or other video processing
applications
Accepts a range of supply voltages for I/O operation. See
Operating Conditions on Page 31
Off-chip voltage regulator interface
349-ball (19 mm × 19 mm) RoHS compliant BGA package
MEMORY
Each core contains 148K bytes of L1 SRAM memory (proces-
sor core-accessible) with multi-parity bit protection
Up to 256K bytes of L2 SRAM memory with ECC protection
Dynamic memory controller provides 16-bit interface to a
single bank of DDR2 or LPDDR DRAM devices
Static memory controller with asynchronous memory inter-
face that supports 8-bit and 16-bit memories
Flexible booting options from flash, eMMC and SPI memories
and from SPI, link port and UART hosts
Memory management unit provides memory protection
EMULATOR
TEST & CONTROL
PLL & POWER
MANAGEMENT
FAULT
MANAGEMENT
SYSTEM CONTROL BLOCKS
EVENT
CONTROL
DUAL
WATCHDOG
PERIPHERALS
2× TWI
8× TIMER
CORE 0
B
148K BYTE
PARITY BIT PROTECTED
L1 SRAM
INSTRUCTION/DATA
CORE 1
B
148K BYTE
PARITY BIT PROTECTED
L1 SRAM
INSTRUCTION/DATA
L2 MEMORY
32K BYTE
ROM
256K BYTE
ECC-
PROTECTED
SRAM
1× COUNTER
2× PWM
3× SPORT
1× ACM
2× UART
112
GP
I/O
EMMC/RSI
DMA SYSTEM
EXTERNAL
BUS
INTERFACES
DYNAMIC
MEMORY
CONTROLLER
STATIC
MEMORY
CONTROLLER
LPDDR
16
DDR2
FLASH
16
SRAM
CRC
HARDWARE
FUNCTIONS
PIPELINED
VISION PROCESSOR
VIDEO
SUBSYSTEM
PIXEL
COMPOSITOR
1× CAN
2× EMAC
WITH
2× IEEE 1588
2× SPI
4× LINK PORT
3× PPI
USB 2.0 HS OTG
Figure 1. Processor Block Diagram
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Rev. PrD
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