ADF7025 Datasheet, PDF (22/44 Pages) Analog Devices – High Performance ISM Band Transceiver IC

ADF7025
LINEAR FSK DEMODULATOR
A block diagram of the linear FSK demodulator is shown in
Figure 30.
ADC RSSI OUTPUT
LEVEL
I
MUX 1
7
SLICER
+
Rx DATA
LIMITER
–
FREQ
Q
0Hz
LINEAR DISCRIMINATOR
DB(6:15)
Figure 30. Block Diagram of Linear FSK Demodulator
This method of frequency demodulation is useful when very
short preamble length is required.
A digital frequency discriminator provides an output signal that
is linearly proportional to the frequency of the limiter outputs.
The discriminator output is then filtered and averaged using a
combined averaging filter and envelope detector. The demodu-
lated FSK data is recovered by threshold-detecting the output of
the averaging filter, as shown in Figure 30. In this mode, the
slicer output shown in Figure 30 is routed to the data synchro-
nizer PLL for clock synchronization. To enable the linear FSK
demodulator, Bits R4_DB [4:5] are set to [00].
The 3 dB bandwidth of the postdemodulation filter is set in the
same way as the FSK correlator/demodulator, which is set in
R4_DB(6:15) and is defined as
Post _ Demod _ BW _ Setting = ^{210 × 2π × FCUTOFF}
DEMOD _ CLK
where:
FCUTOFF is the target 3 dB bandwidth in Hz of the
postdemodulator filter.
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section.
AUTOMATIC SYNC WORD RECOGNITION
The ADF7025 also supports automatic detection of the sync or
ID fields. To activate this mode, the sync (or ID) word must be
preprogrammed into the ADF7025. In receive mode, this
preprogrammed word is compared to the received bit stream
and, when a valid match is identified, the external pin
INT/LOCK is asserted by the ADF7025.
This feature can be used to alert the microprocessor that a valid
channel has been detected. It relaxes the computational require-
ments of the microprocessor and reduces the overall power
consumption. The INT/LOCK is automatically de-asserted
again after nine data clock cycles.
The automatic sync/ID word detection feature is enabled by
selecting Demod Mode 2 or Demod Mode 3 in the demodulator
setup register. Do this by setting R4_DB [25:23] = [010] or
R4_DB [25:23] = [011]. Bits R5_DB [4:5] are used to set the
length of the sync/ID word, which can be either 12 bits, 16 bits,
20 bits, or 24 bits long. The transmitter must transmit the MSB
of the sync byte first and the LSB last to ensure proper
alignment in the receiver sync byte detection hardware.
For systems using FEC, an error tolerance parameter can also
be programmed that accepts a valid match when up to three bits
of the word are incorrect. The error tolerance value is assigned
in R5_DB [6:7].
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