AD9753ASTZ Datasheet, PDF (22/28 Pages) Analog Devices – 12-Bit, 300 MSPS High Speed TxDAC+ D/A Converter

AD9753
2 P1
4 P1
6 P1
8 P1
10 P1
12 P1
14 P1
16 P1
P1 1
P1 3
P1 5
P1 7
P1 9
P1 11
P1 13
P1 15
RN1
VALUE
1B13 1 16
1B12 2 15
1B11 3 14
1B10 4 13
1B09 5 12
1B08 6 11
1B07 7 10
1B06 8 9
RN2
VALUE
1
P1B13 2
P1B12 3
P1B11 4
P1B10 5
P1B09 6
P1B08 7
P1B07 8
P1B06 9
10
1B13
1B12
1B11
1B10
1B09
1B08
1B07
1B06
RN3
VALUE
1
2
3
4
5
6
7
8
9
10
RN4
VALUE
RN5
VALUE
1
RN6
VALUE
1
18 P1
20 P1
22 P1
24 P1
26 P1
28 P1
30 P1
32 P1
34 P1
36 P1
38 P1
40 P1
P1 17 ^{1B05 1 16}
P1 19 ^{1B04 2 15}
P1 21 ^{1B03 3 14}
P1 23 ^{1B02 4 13}
P1 25 ^{1B01 5 12}
P1 27 ^{1B00 6 11}
P1 29 ^{1O17 7 10}
P1 31
89
P1 33
1O15
P1 35 _1O16
P1 37
P1 39
RN7
VALUE
P1B05
P1B04
P1B03
P1B02
P1B01
P1B00
OUT15
OUT16
2
1B05 ²
3
3
1B04
4
4
1B03
5
1B02 ⁵
6
6
1B01
7
1B00 ⁷
8
8
1O15
9
1O16 ₉
JP10
10
10
1O17
RN8
VALUE
1
RN9
VALUE
1
2 P2
4 P2
6 P2
8 P2
10 P2
12 P2
14 P2
16 P2
P2 1 ^{2B13 1}
P2 3 ^{2B12 2}
P2 5 ^{2B11 3}
P2 7 ^{2B10 4}
P2 9 ^{2B09 5}
P2 11 ^{2B08 6}
P2 13 ^{2B07 7}
P2 15 ^{2B06 8}
16 P2B13 2
15 P2B12 3
14 P2B11 4
13 P2B10 5
12 P2B09 6
11 P2B08 7
10 P2B07 8
9 P2B06 9
10
2B13 ²
3
2B12
2B11 ⁴
2B10 ⁵
2B09 ⁶
7
2B08
8
2B07
2B06 ⁹
10
18 P2
20 P2
22 P2
24 P2
26 P2
28 P2
30 P2
32 P2
34 P2
RN10
VALUE
RN11
VALUE
1
P2 17 ^{2B05 1}
P2 19 ^{2B04 2}
2B03 ₃
P2 21
2B02 ₄
P2 23
2B01 ₅
P2 25
2B00 ₆
P2 27
7
P2 29
8
P2 31
P2 33
16 P2B05 2
15 P2B04 3
14 P2B03 4
13 P2B02 5
12 P2B01 6
11 P2B00 7
10 P2OUT15 8
9 P2OUT16 9
10
36 P2 P2 35
38 P2 P2 37
40 P2 P2 39
2B05
2B04
2B03
2B02
2B01
2B00
2OUT15
2OUT16
RN12
VALUE
1
2
3
4
5
6
7
8
9
10
OUT16
DVDD PLANE
J1
1
DGND: 3,4,5 2
P1B13 MSB
P1B12
P1B11
CLK–
CLK+
EDGE
1
2A
EXT ^B
JP5
3
RESET
TP3
R4 ^WHT
50⍀
P
P1B10
P1B09
RESET
PLLVDD PLANE
P1B08
12 11 10 9 8 7 6 5 4 3 2 1
C11
P1B07
13
48 CLKVDD
1.0␮F
P1B06
14
P1B05
15
47
46 ^LPF
R5
392⍀
P1B04
16
45
P1B03
17
44
P1B02
18
U1
43 ^IA
P1B01 _{19 AD9751/AD9753/AD9755 42} IB
P1B00LSB ₂₀
41 AVDD PLANE
NOTE:
SHIELD AROUND
R5 AND C11 ARE
CONNECTED TO
PLLVDD PLANE
DVDD PLANE
MSB
P2B13
P2B12
P2B11
21
40
22
39
23
38
24
37
25 26 27 28 29 30 31 32 33 34 35 36
R3
50⍀
C10
10pF
R10
OPT
R2
50⍀
C9
10pF
P2B10
P2B09
P2B08
P2B07
P2B06
P2B05
BL1
I_OUT
J5
1
3 ^T1
2
4
P2B04
2
P2B03
P2B02
P2B01
6
1
P
S
P2B00 LSB
TP1
R1
FSADJ WHT 1.91k⍀
BL2
NOTES
1. ALL DIGITAL INPUTS FROM RN1–RN12
MUST BE OF EQUAL LENGTH.
2. ALL DECOUPLING CAPS TO BE LOCATED
AS CLOSE AS POSSIBLE TO DUT,
PREFERABLY UNDER DUT ON BOTTOM
SIGNAL LAYER.
3. CONNECT GNDS UNDER DUT USING
BOTTOM SIGNAL LAYER.
4. CREATE PLANE CAPACITOR WITH 0.007"
DIELECTRIC BETWEEN LAYERS 2 AND 3.
TP2
C12
REFIO
0.1␮F
WHT
JP8
1
3
AB
DIV1 ²
JP9
1
3
AB
DIV0 2
AVDD_PLANE
TP4 TP5 TP6
BLK BLK BLK
TP7 TP8 TP9
BLK BLK BLK
TP10 TP12
BLK BLK
P
Figure 34. Evaluation Board Circuitry
–22–
REV. B