AD8403_15 Datasheet, PDF (22/32 Pages) Analog Devices – Digital Potentiometers

AD8400/AD8402/AD8403
CS
V_DD
CLK
D7
A1
EN
RDAC
W1
LATCH
ADDR
NO. 1
R
B1
SDO
A1
DO _A0
DEC
D0
D7
SER
REG
AD8403
A4
SDI
DI _D0
D7
RDAC
W4
LATCH
NO. 4
B4
8
R
D0
SHDN
DGND
RS
AGND
Figure 48. AD8403 Block Diagram
Table 12. Input Logic Control Truth Table¹
CLK CS RS SHDN Register Activity
L L HH
No SR effect; enables SDO pin
P L HH
Shift one bit in from the SDI pin. The
10th previously entered bit is shifted
out of the SDO pin.
X P HH
Load SR data into RDAC latch based
on A1, A0 decode (Table 13).
X HHH
No operation
X XLH
Sets all RDAC latches to midscale,
wiper centered, and SDO latch
cleared
X HP H
X HHL
Latches all RDAC latches to 80H
Open-circuits all Resistor A terminals,
connects W to B, turns off SDO
output transistor.
1 _{P = positive edge, X = don’t care, SR = shift register}
The serial data output (SDO) pin, which exists only on the
AD8403 and not on the AD8400 or AD8402, contains an
open-drain, n-channel FET that requires a pull-up resistor to
transfer data to the SDI pin of the next package. The pull-up
resistor termination voltage may be larger than the VDD supply
(but less than the max VDD of 8 V) of the AD8403 SDO output
device. For example, the AD8403 could operate at VDD = 3.3 V,
and the pull-up for interface to the next device could be set at 5 V.
This allows for daisy-chaining several RDACs from a single proc-
essor serial data line. The clock period needs to be increased
when using a pull-up resistor to the SDI pin of the following
device in the series. Capacitive loading at the daisy-chain node
SDO to SDI between devices must be accounted for in order to
transfer data successfully. When daisy chain is used, CS should
be kept low until all the bits of every package are clocked into
their respective serial registers and the address and data bits are
in the proper decoding location.
If two AD8403 RDACs are daisy-chained, it requires 20 bits
of address and data in the format shown in Table 6. During
shutdown (SHDN = logic low), the SDO output pin is forced
to the off (logic high) state to disable power dissipation in the
pull-up resistor. See Figure 50 for equivalent SDO output circuit
schematic.
The data setup and hold times in the specification table deter-
mine the data valid time requirements. The last 10 bits of the
data-word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder, which enables one of the two (AD8402) or four (AD8403)
positive edge-triggered RDAC latches. See Figure 49 and Table 13.
Table 13. Address Decode Table
A1
A0
Latch Decoded
0
0
RDAC#1
0
1
RDAC#2
1
0
RDAC#3 AD8403 Only
1
1
RDAC#4 AD8403 Only
AD8403
CS
CLK
SDI
ADDR
DECODE
RDAC 1
RDAC 2
RDAC 4
SERIAL
REGISTER
Figure 49. Equivalent Input Control Logic
The target RDAC latch is loaded with the last eight bits of the
serial data-word completing one RDAC update. In the case of
AD8403, four separate 10-bit data-words must be clocked in to
change all four VR settings.
SHDN
CS
SDI
CLK
RS
SERIAL
REGISTER
DQ
CK RS
SDO
Figure 50. Detailed SDO Output Schematic of the AD8403
All digital pins are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 51. This structure
applies to digital pins CS, SDI, SDO, RS, SHDN, and CLK. The
digital input ESD protection allows for mixed power supply
applications where 5 V CMOS logic can be used to drive an
AD8400, AD8402, or AD8403 operating from a 3 V power
supply. Analog Pin A, Pin B, and Pin W are protected with a
20 Ω series resistor and parallel Zener diode (see Figure 52).
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