AD8403_15 Datasheet, PDF (12/32 Pages) Analog Devices – Digital Potentiometers

AD8400/AD8402/AD8403
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
B1 1
GND 2
CS 3
SDI 4
AD8400
TOP VIEW
(Not to Scale)
8 A1
7 W1
6 V_DD
5 CLK
Figure 6. AD8400 Pin Configuration
AGND 1
B2 2
A2 3
W2 4
DGND 5
SHDN 6
CS 7
AD8402
TOP VIEW
(Not to Scale)
14 B1
13 A1
12 W1
11 V_DD
10 RS
9 CLK
8 SDI
Figure 7. AD8402 Pin Configuration
AGND2 1
B2 2
A2 3
W2 4
AGND4 5
B4 6
A4 7
W4 8
DGND 9
SHDN 10
CS 11
SDI 12
AD8403
TOP VIEW
(Not to Scale)
24 B1
23 A1
22 W1
21 AGND1
20 B3
19 A3
18 W3
17 AGND3
16 V_DD
15 RS
14 CLK
13 SDO
Figure 8. AD8403 Pin Configuration
Table 7. AD8400 Pin Function Descriptions
Pin No. Mnemonic Description
1
B1
Terminal B RDAC.
2
GND
Ground.
3
CS
Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
4
SDI
Serial Data Input.
5
CLK
Serial Clock Input, Positive Edge Triggered.
6
VDD
Positive Power Supply. Specified for operation at both 3 V and 5 V.
7
W1
Wiper RDAC, Addr = 002.
8
A1
Terminal A RDAC.
Table 8. AD8402 Pin Function Descriptions
Pin No. Mnemonic Description
1
AGND
Analog Ground.¹
2
B2
Terminal B RDAC 2.
3
A2
Terminal A RDAC 2.
4
W2
Wiper RDAC 2, Addr = 012.
5
DGND
Digital Ground.¹
6
SHDN
Terminal A Open Circuit. Shutdown controls Variable Resistor 1 and Variable Resistor 2.
7
CS
Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
8
SDI
Serial Data Input.
9
CLK
Serial Clock Input, Positive Edge Triggered.
10
RS
Active Low Reset to Midscale. Sets RDAC registers to 80H.
11
VDD
Positive Power Supply. Specified for operation at both 3 V and 5 V
12
W1
Wiper RDAC 1, Addr = 002.
13
A1
Terminal A RDAC 1.
14
B1
Terminal B RDAC 1.
1 _{All AGND pins must be connected to DGND.}
Rev. E | Page 12 of 32