AD9782 Datasheet, PDF (21/52 Pages) Analog Devices – 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2 x /4 x /8 x Interpolation and Signal Processing

Preliminary Technical Data
AD9782
Table 15.
PLL(04)
PLLON
PLLMULTI[1:0]
PLLDIV[1:0]
PLLAZBW[1:0]
PLOCKEXT
Bit Direction Default Description
7
I
0
0: PLL off
1: PLL on
[6:5] I
00
PLL MULTIPLY FACTOR
00: ×2
00: ×4
00: ×8
00: ×16
[4:3] I
00
PLLMULT rate divide factor
00:/1
00:/2
00:/4
00:/8
[2:1] I
00
PLL Autozero settling bandwidth as fraction of CLK ±rate
00: /8 (lowest)
01: /4
10: /2 (highest)
0
I
0
0: With PLL on, DATACLK/PLL_LOCK pin configured for DATACLK input/output
1: With PLL on, DATACLK/PLL_LOCK pin configured for output of PLLLOCK
Table 16.
DCLKCRC(05)
DATADJ[3:0]
MODSYNC
MODADJ[2:0]
Bit Direction
[7:4] I
3
I
[2:0] I
Default
0000
00
000
Description
DATACLK offset. Twos complement respresentation
0111: +7
:
0000: 0
:
1000: -8
0: With PLOCKEXT off, channel data rate clock synchronizer mode
1: With PLOCKEXT off, state machine clock synchronizer mode
fS/8
fS/4 fS/2 Modulator coefficient offset
000 1
1
1
001 1/√2
0
–1
010 0
–1
1
011 –1/√2
0
–1
100 –1
1
1
101 –1/√2
0
–1
110 0
–1
1
111 1/√2
0
–1
Table 17.
VERSION(0D)
VERSION[3:0]
Bit
Direction
[3:0]
O
Default
–
Description
Hardware version identifier
Rev. PrC | Page 21 of 52