AD9523BCPZ Datasheet, PDF (20/60 Pages) Analog Devices – Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs

AD9523
Data Sheet
THEORY OF OPERATION
DETAILED BLOCK DIAGRAM
VDD3_PLL1 LDO_PLL1
LF1_EXT_CAP
VCXO
OSC_CTRL OSC_IN
PLL1_OUT
STATUS0/
SP0
STATUS1/
SP1 _{LF2_EXT_CAP}
LDO_VCO ^{VDD1.8_OUT[x:y] VDD3_OUT[x:y]}
REFA
REFA
REF_SEL
REFB
REFB
REF_TEST
SDIO/SDA
SDO
SCLK/SCL
CS
RESET
PD
EEPROM_SEL
LOCK
÷R
DETECT
SWITCH-
OVER
LOOP
CONTROL
÷R
FILTER
P
F
D
CHARGE
PUMP
÷R
÷N1
CONTROL
INTERFACE
(SDI AND I²C)
EEPROM
AD9523
STATUS MONITOR
LOCK DETECT/
SERIAL PORT
ADDRESS
÷D1
LOCK
DETECT
SYNC
SIGNAL
×2
P
F
D
CHARGE
PUMP
LOOP
FILTER
VCO
÷M1
PLL1
÷N2
PLL2
TO SYNC
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
÷D
∆t
EDGE
OUT13
OUT13
OUT12
OUT12
OUT11
OUT11
OUT10
OUT10
OUT9
OUT9
OUT8
OUT8
OUT7
OUT7
OUT6
OUT6
OUT5
OUT5
OUT4
OUT4
OUT3
OUT3
OUT2
OUT2
OUT1
OUT1
OUT0
OUT0
ZD_IN
ZD_IN
LDO_PLL2
VDD3_PLL2
NC
Figure 22. Top Level Diagram
SYNC
OVERVIEW
The AD9523 is a clock generator that employs integer-N-based
phase-locked loops (PLL). The device architecture consists of
two cascaded PLL stages. The first stage, PLL1, consists of an
integer division PLL that uses an external voltage-controlled
crystal oscillator (VCXO) from 15 MHz to 250 MHz. PLL1 has
a narrow-loop bandwidth that provides initial jitter cleanup of the
input reference signal. The second stage, PLL2, is a frequency
multiplying PLL that translates the first stage output frequency
to a range of 3.6 GHz to 4.0 GHz. PLL2 incorporates an integer-
based feedback divider that enables integer frequency multipli-
cation. Programmable integer dividers (1 to 1024) follow PLL2,
establishing a final output frequency of 1 GHz or less.
The AD9523 includes reference signal processing blocks that
enable a smooth switching transition between two reference
inputs. This circuitry automatically detects the presence of the
reference input signals. If only one input is present, the device
uses it as the active reference. If both are present, one becomes
the active reference and the other becomes the backup reference.
If the active reference fails, the circuitry automatically switches
to the backup reference (if available), making it the new active
reference. A register setting determines what action to take if
the failed reference is once again available: either stay on
Reference B or revert to Reference A. If neither reference can
be used, the AD9523 supports a holdover mode. A reference
select pin (REF_SEL, Pin 16) is available to manually select
which input reference is active (see Table 43). The accuracy of the
holdover is dependent on the external VCXO frequency
stability at half supply voltage.
Any of the divider settings are programmable via the serial
programming port, enabling a wide range of input/output
frequency ratios under program control. The dividers also
include a programmable delay to adjust timing of the output
signals, if required.
The output is compatible with LVPECL, LVDS, or HSTL logic
levels (see the Input/Output Termination Recommendations
section); however, the AD9523 is implemented only in CMOS.
The loop filters of each PLL are integrated and programmable.
Only a single external capacitor for each of the two PLL loop
filters is required.
The AD9523 operates over the extended industrial temperature
range of −40°C to +85°C.
Rev. C | Page 20 of 60