DAC8412 Datasheet, PDF (2/14 Pages) Analog Devices – Quad, 12-Bit DAC Voltage Output with Readback

DAC8412/DAC8413–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VDD = +15.0 V, VSS = –15.0 V, VLOGIC = +5.0 V, VREFH = +10.0 V, VREFL = –10.0 V,
–40؇C ≤ T_A ≤ +85؇C unless otherwise noted. See Note 1 for supply variations.)
Parameter
Integral Nonlinearity Error
Differential Nonlinearity Error
Min-Scale Error
Full-Scale Error
Min-Scale Tempco
Full-Scale Tempco
Linearity Matching
Symbol Conditions
Min
INL
E Grade
INL
F Grade
DNL
Monotonic Over Temperature –1
V_ZSE
V_FSE
TCV_ZSE
TCV_FSE
R_L = 2 kΩ
R_L = 2 kΩ
R_L = 2 kΩ
R_L = 2 kΩ
Adjacent DAC Matching
Typ Max
0.25 ± 0.5
±1
±2
±2
15
20
±1
Units
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
REFERENCE
Positive Reference Input Voltage Range
Negative Reference Input Voltage Range
Reference High Input Current
Reference Low Input Current
Large Signal Bandwidth
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
Slew Rate
Analog Crosstalk
I_REFH
I_REFL
BW
I_OUT
t_S
SR
Note 2
Note 2
–3 dB, V_REFH = 0 V to +10 V p-p
V_REFL + 2.5
–10
–2.75
+1.5
0
+2
160
R_L = 2 kΩ, C_L = 100 pF
–5
to 0.01%, 10 V Step, R_L = 1 kΩ
10
10% to 90%
2.2
72
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Output High Voltage
Logic Output Low Voltage
Logic Input Current
Input Capacitance
Digital Feedthrough³
V_INH
T_A = +25°C
2.4
V_INL
T_A = +25°C
V_OH
I_OH = +0.4 mA
2.4
V_OL
I_OL = –1.6 mA
I_IN
C_IN
8
V_REFH = +2.5 V, V_REFL = 0 V
5
LOGIC TIMING CHARACTERISTICS³
Note 4
Chip Select Write Pulsewidth
t_WCS
80
Write Setup
t_WS
t_WCS = 80 ns
0
Write Hold
t_WH
t_WCS = 80 ns
0
Address Setup
t_AS
0
Address Hold
t_AH
0
Load Setup
t_LS
70
Load Hold
t_LH
30
Write Data Setup
t_WDS
t_WCS = 80 ns
20
Write Data Hold
t_WDH
t_WCS = 80 ns
0
Load Data Pulsewidth
t_LDW
170
Reset Pulsewidth
t_RESET
140
Chip Select Read Pulsewidth
t_RCS
130
Read Data Hold
t_RDH
t_RCS = 130 ns
0
Read Data Setup
t_RDS
t_RCS = 130 ns
0
Data to Hi Z
t_DZ
C_L = 10 pF
Chip Select to Data
t_CSD
C_L = 100 pF
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
PSS
14.25 V ≤ V_DD ≤ 15.75 V
I_DD
V_REFH = +2.5 V
8.5
I_SS
–10
–6.5
P_DISS
NOTES
1_{All supplies can be varied ± 5%, and operation is guaranteed. Device is tested with nominal supplies.}
2_{Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.}
3_{All parameters are guaranteed by design.}
4_{All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.}
Specifications subject to change without notice.
V_DD – 2.5 V
V_REFH – 2.5 V
+2.75
mA
+2.75
mA
kHz
+5
mA
µs
V/µs
dB
V
0.8
V
V
0.4
V
1
µA
pF
nV-s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
ns
160
ns
150
ppm/V
12
mA
mA
330
mW
–2–
REV. D