CN0337 Datasheet, PDF (2/8 Pages) Analog Devices – EVALUATION AND DESIGN SUPPORT

CN-0337
CIRCUIT DESCRIPTION
The input stage of the circuit is an RTD signal conditioning circuit
using a compensated 3-wire connection to the RTD. The circuit
translates the RTD input resistance range (100 Ω to 212.05 Ω
for a 0°C to 300°C temperature range) into voltage levels
compatible with the input range of the ADC (0 V to 2.5 V).
The excitation current for the RTD is supplied by op amp U1C
that is one-fourth of the quad AD8608. A reference voltage, VR,
of 100 mV is developed by the R8/R9 divider driven by the 2.5 V
ADC reference. This in turn produces an RTD excitation
current of VR/(R1||R2), approximately 1.05 mA.
The excitation current produces a voltage change of
approximately 117.6 mV (105 mV to 222.6 mV) across the RTD
for a temperature change of 0°C to 300°C. The U1A op amp
amplifies this voltage change by 19.6, producing an output span
of 2.3 V. Resistor R2 added in parallel with Resistor R1 shifts the
output range so that the U1A op amp output is 0.1 V to 2.4 V,
which matches the input range of the ADC (0 V to 2.5 V) with
100 mV headroom to maintain linearity. The resistor values can
be modified to accommodate other popular temperature ranges
as described later in this circuit note.
The circuit design allows single supply operation. The minimum
output voltage specification for the AD8608 is 50 mV for a 2.7 V
power supply and 290 mV for a 5 V power supply with 10 mA
load current, over the temperature range of −40°C to +125°C.
A minimum output voltage of 45 mV to 60 mV is a conservative
estimate for a 3.3 V power supply, a load current of less than
1 mA, and a narrower temperature range.
Considering the tolerances of the parts, the minimum output
voltage (low limit of the range) is set to 100 mV to allow for a
safety margin. The upper limit of the output range is set to 2.4 V
in order to give 100 mV headroom for the positive swing at the
ADC input. Therefore, the nominal output voltage range of the
op amp is 0.1 V to 2.4 V.
The op amp U1B is used to buffer the internal 2.5 V voltage
reference of the AD7091R (U3) ADC.
The quad AD8608 op amp is chosen for this application because of
its low offset voltage (75 µV maximum), low bias current (1 pA
maximum), and low noise (12 nV/√Hz maximum). Power
dissipation is only 18.5 mW on a 3.3 V supply.
The U1D op amp provides the 3-wire correction signal that
compensates for the errors produced by the lead resistances r1
and r2. The gain from Point A to TP1 is +19.6, and the gain
from Point B to TP1 is −39.2. The voltage at Point A includes a
positive error term that is equal to the voltage dropped across r1
and r2. The voltage at Point B contains a positive error term
equal to the voltage dropped across r2, neglecting the small drop
across r3. Because the gain from Point B to TP1 is negative and
twice the gain from Point A to TP1, the errors due to the voltages
dropped across r1 and r2 are cancelled, assuming that r1 = r2.
Circuit Note
A single-pole RC filter (R11/C9) follows the op amp output
stage to reduce the out-of-band noise. The cutoff frequency of
the RC filter is set to 664 kHz. Additional second order filters
(adding capacitors C10 and C11) are used for reducing the filter
cutoff frequency in case of low frequency industrial noise. In
this case, AD7091R is not operating at maximum throughput
rate. To increase the conversion speed C10 and C11 should be
left unpopulated.
The AD7091R 12-bit 1 MSPS SAR ADC is chosen because of its
ultralow power 349 μA at 3.3 V (1.2 mW) which is significantly
lower than any competitive ADC currently available in the market.
The AD7091R also contains an internal 2.5 V reference with
±4.5 ppm/^oC typical drift. The input bandwidth is 7.5 MHz,
and the high speed serial interface is SPI compatible. The
AD7091R is available in a small footprint 10-lead MSOP.
The total power dissipation of the circuit (excluding the
ADuM5401 isolator) is approximately 20 mW when operating
on a 3.3 V supply.
Galvanic isolation is provided by the ADuM5401 (C Grade) quad
channel digital isolator. In addition to the isolated output data,
the ADuM5401 also provides isolated +3.3 V for the circuit.
The ADuM5401 is not required for normal circuit operation
unless isolation is needed. The ADuM5401 quad-channel,
2.5 kV isolators with integrated dc-to-dc converter, is available
in a small 16-lead SOIC. Power dissipation of the ADuM5401
with a 7 MHz clock is approximately 140 mW.
The AD7091R requires a 50 MHz serial clock (SCLK) to achieve
a 1 MSPS sampling rate. However, the ADuM5401 (C-grade)
isolator has a maximum data rate of 25 Mbps that corresponds
to a maximum serial clock frequency of 12.5 MHz. In addition,
the SPI port requires that the trailing edge of the SCLK clock
the output data into the processor, therefore the total round-trip
propagation delay through the ADuM5401 (120 ns maximum)
limits the upper clock frequency to 1/120 ns = 8.3 MHz.
Even though the AD7091R is a 12-bit ADC, the serial data is
formatted into a 16-bit word to be compatible with the
processor serial port requirements. The sampling period, TS,
therefore consists of the AD7091R 650 ns conversion time plus
58 ns (extra time required from data sheet, t1 delay + tQUIET
delay) plus 16 clock cycles for the SPI interface data transfer.
TS = 650 ns + 58 ns + 16 × 120 ns = 2628 ns
fS = 1/TS = 1/2628 ns = 380 kSPS
In order to provide a safety margin, a maximum SCLK of
7 MHz and a maximum sampling rate of 300 kSPS is
recommended. The digital SPI interface can be connected to the
microprocessor evaluation board using the 12-pin Pmod-
compatible connector (Digilent Pmod Specifications).
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