CN-0046 Datasheet, PDF (2/3 Pages) Analog Devices – Using the AD8352 as an Ultralow Distortion Differential RF/IF Front End for High Speed ADCs

CN-0046
5V
50Ω
AC
0.1µF
VIP
64.9Ω
C_D
R_D R_G
VOP ^0.1µF 33Ω
AD8352
24.9Ω ^0.1µF
VIN
R_N
200Ω
0.1µF
33Ω
VON 0.1µF
VIN+
AD9445
VIN–
Figure 2. Single-Ended Input to the AD8352 Driving the AD9445 ADC
(Simplified Schematic, All Connections Not Shown)
Circuit Note
differential FFT plots in Figure 3 and Figure 4. The single-
ended circuit avoids the use of a transformer or balun in
front of the amplifier while still maintaining excellent
distortion up to approximately 100 MHz. However, at
frequencies above approximately 100 MHz, second-order
distortion increases when the AD8352 is driven single-ended
due to phase-related errors.
0
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0
SNR = 67.26dBc
SFDR = 83.18dBc
NOISE FLOOR = –110.5dB
FUND = –1.074dBFS
SECOND = –83.14dBc
THIRD = –85.39dBc
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
Figure 3. Single Tone Distortion, AD8352 Driving AD9445, Sampling Clock = 105 MSPS,
Analog Input Frequency = 100 MHz, AV = 10 dB. See Figure 1.
In both configurations, RG is the gain setting resistor for the
AD8352, with the RD and CD components providing
distortion cancellation. The AD9445 differential input
impedance is approximately 2 kΩ in parallel with 5 pF and
requires a 2.0 V p-p differential signal (VREF = 1 V) between
VIN+ and VIN− for a full-scale input signal.
The output of the amplifier is ac-coupled to allow for an
optimum common-mode voltage at the ADC input. The
common-mode voltage at the input of the AD9445 is set to
3.5 V by an internal network. Input ac-coupling can be
required if the source also requires a common-mode voltage
that is outside the optimum range of the AD8352. A VCM
common-mode pin is provided on the AD8352 that equally
shifts both input and output common-mode levels. Increasing
the gain of the AD8352 increases the system noise and, thus,
decreases the SNR (3.5 dB at 100 MHz input for AV = 10 dB) of
the AD9445 when no filtering is used. However, it should be
noted that amplifier gains from 3 dB to 18 dB, with proper
selection of CD and RD, do not appreciably affect distortion
levels. These circuits, when configured properly, can result in
SFDR performance of better than 87 dBc at 70 MHz and 82 dBc
at 180 MHz input. Single-ended drive, with appropriate CD and
RD, gives similar results for SFDR and third-order intermodulation
levels as shown in these figures.
Excellent layout, grounding, and decoupling techniques must be
utilized in order to achieve the desired performance from the
circuits discussed in this note. As a minimum, a 4-layer PCB
should be used with one ground plane layer, one power plane
layer, and two signal layers.
All IC power pins must be decoupled to the ground plane
with low inductance multilayer ceramic capacitors (MLCC)
of 0.01 µF to 0.1 µF (this is not shown in the diagrams for
simplicity). Follow the recommendations on the individual
data sheets for the ICs.
The product evaluation boards should be consulted for
recommended layout and critical component placement. They
can be accessed through the main product pages for the devices
or their data sheets.
0
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0
SNR = 61.98dBc
NOISE FLOOR = –111.2dB
FUND1 = –7.072dBFS
FUND2 = –7.043dBFS
IMD (2F2-F1) = –89dBc
IMD (2F1-F2) = –88dBc
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
Figure 4. Two Tone Intermodulation Distortion, AD8352 Driving AD9445,
Sampling Clock = 105 MSPS, Analog Input Frequency = 98 MHz and
101 MHz, AV = 10 dB. See Figure 1.
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