AD5305 Datasheet, PDF (2/20 Pages) Analog Devices – 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs

AD5305/AD5315/AD5325–SPECIFICATIONS (V_DD = 2.5 V to 5.5 V; V_REF = 2 V; R_L = 2 k⍀ to GND;
C_L = 200 pF to GND; all specifications T_MIN to T_MAX, unless otherwise noted.)
Parameter¹
A Version²
Min
Typ
Max
B Version²
Min
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE^{3, 4}
AD5305
Resolution
Relative Accuracy
Differential Nonlinearity
AD5315
Resolution
Relative Accuracy
Differential Nonlinearity
AD5325
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
Offset Error Drift⁵
Gain Error Drift⁵
Power Supply Rejection Ratio⁵
DC Crosstalk⁵
DAC REFERENCE INPUTS⁵
V_REF Input Range
0.25
V_REF Input Impedance
37
Reference Feedthrough
8
± 0.15
± 0.02
10
± 0.5
± 0.05
12
±2
± 0.2
± 0.4
± 0.15
20
–12
–5
–60
200
45
>10
–90
±1
± 0.25
8
± 0.15
± 0.02
10
±4
± 0.5
± 0.5
± 0.05
12
± 16
±2
±1
± 0.2
±3
± 0.4
±1
± 0.15
60
20
–12
–5
–60
200
V_DD
0.25
37
45
>10
–90
± 0.625
± 0.25
± 2.5
± 0.5
± 10
±1
±3
±1
60
Bits
LSB
LSB
Guaranteed Monotonic by Design
over All Codes
Bits
LSB
LSB
Guaranteed Monotonic by Design
over All Codes
Bits
LSB
LSB
Guaranteed Monotonic by Design
over All Codes
% of FSR
% of FSR
mV
Lower deadband exists only if
offset error is negative.
ppm of FSR/°C
ppm of FSR/°C
dB
⌬V_DD = ± 10%
µV
R_L = 2 kΩ to GND or V_DD
V_DD
V
kΩ
MΩ
dB
Normal Operation
Power-Down Mode
Frequency = 10 kHz
OUTPUT CHARACTERISTICS⁵
Minimum Output Voltage⁶
Maximum Output Voltage⁶
DC Output Impedance
Short Circuit Current
Power-Up Time
0.001
V_DD – 0.001
0.5
25
16
2.5
5
0.001
V
V_DD – 0.001
V
0.5
Ω
25
mA
16
mA
2.5
µs
5
µs
LOGIC INPUTS (A0)⁵
Input Current
V_IL, Input Low Voltage
V_IH, Input High Voltage
Pin Capacitance
2.4
2.1
2.0
3
±1
0.8
0.6
0.5
2.4
2.1
2.0
3
±1
µA
0.8
V
0.6
V
0.5
V
V
V
V
pF
This is a measure of the minimum
and maximum drive capability
of the output amplifier.
V_DD = 5 V
V_DD = 3 V
Coming out of Power-Down Mode.
V_DD = 5 V
Coming out of Power-Down Mode.
V_DD = 3 V
V_DD = 5 V ± 10%
V_DD = 3 V ± 10%
V_DD = 2.5 V
V_DD = 5 V ± 10%
V_DD = 3 V ± 10%
V_DD = 2.5 V
LOGIC INPUTS (SCL, SDA)⁵
V_IH, Input High Voltage
V_IL, Input Low Voltage
I_IN, Input Leakage Current
V_HYST, Input Hysteresis
C_IN, Input Capacitance
Glitch Rejection
0.7 V_DD
–0.3
0.05 V_DD
8
V_DD + 0.3 0.7 V_DD
0.3 V_DD –0.3
±1
0.05 V_DD
8
50
V_DD + 0.3 V
0.3 V_DD V
±1
µA
V
pF
50
ns
SMBus Compatible at V_DD < 3.6 V
SMBus Compatible at V_DD < 3.6 V
Input filtering suppresses noise
spikes of less than 50 ns.
LOGIC OUTPUT (SDA)⁵
V_OL, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
0.4
0.6
±1
8
0.4
V
0.6
V
±1
µA
8
pF
I_SINK = 3 mA
I_SINK = 6 mA
–2–
REV. F