AD5305 Datasheet, PDF (1/20 Pages) Analog Devices – 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs

2.5 V to 5.5 V, 500 ␮A, 2-Wire Interface
Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305/AD5315/AD5325^*
FEATURES
AD5305: 4 Buffered 8-Bit DACs in 10-Lead MSOP
A Version: ؎1 LSB INL, B Version: ؎0.625 LSB INL
AD5315: 4 Buffered 10-Bit DACs in 10-Lead MSOP
A Version: ؎4 LSB INL, B Version: ؎2.5 LSB INL
AD5325: 4 Buffered 12-Bit DACs in 10-Lead MSOP
A Version: ؎16 LSB INL, B Version: ؎10 LSB INL
Low Power Operation: 500 ␮A @ 3 V, 600 ␮A @ 5 V
2-Wire (I²C^® Compatible) Serial Interface
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic by Design over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Three Power-Down Modes
Double-Buffered Input Logic
Output Range: 0 V to V_REF
Power-On Reset to 0 V
Simultaneous Update of Outputs (LDAC Function)
Software Clear Facility
Data Readback Facility
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40؇C to +105؇C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5305/AD5315/AD5325 are quad 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 500 µA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/µs. A 2-wire serial interface, which
operates at clock rates up to 400 kHz, is used. This interface is
SMBus compatible at V_DD < 3.6 V. Multiple devices can be
placed on the same bus.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on reset circuit, which ensures that the DAC outputs power
up to 0 V and remain there until a valid write takes place to the
device. There is also a software clear function that resets all input
and DAC registers to 0 V. The parts contain a power-down
feature that reduces the current consumption of the devices to
200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1 µW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
LDAC
V_DD
REF IN
INPUT
REGISTER
DAC
REGISTER
STRING _BUFFER
DAC A
V_OUTA
SCL
SDA
A0
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING _BUFFER
DAC B
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
V_OUTB
V_OUTC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
V_OUTD
POWER-ON
RESET
AD5305/AD5315/AD5325
POWER-DOWN
LOGIC
GND
*Protected by U.S.Patent No. 5,969,657and 5,684,481.
REV. F
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