ADSP-BF535 Datasheet, PDF (19/44 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF535
Table 7. Pin Descriptions (continued)
Pin
TRST
Type Function
I
JTAG reset.
RESET
CLKIN1
BYPASS
DEEPSLEEP
BMODE2 – 0
PCI_AD31 – 0
PCI_CBE3–0
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_DEVSEL
PCI_STOP
PCI_PERR
PCI_PAR
PCI_REQ
PCI_SERR
PCI_RST
PCI_GNT
PCI_IDSEL
PCI_LOCK
PCI_CLK
PCI_INTA
PCI_INTB
PCI_INTC
PCI_INTD
XTAL1
XTAL0
EMU
V_DDPLL
V_DDRTC
V_DDEXT
V_DDPCIEXT
V_DDINT
GND
I
When this pin is asserted to logic zero level for at least 10 CLKIN cycles, a hardware reset
is initiated. The minimum pulse width for power-on reset is 40 µs.
I
Clock in.
I
Dedicated mode pin. May be permanently strapped to V_DD or V_SS. Bypasses the on-chip
PLL.
O Denotes that the Blackfin processor core is in Deep Sleep mode.
I
Dedicated mode pin. May be permanently strapped to V_DD or V_SS. Configures the boot
mode that is employed following hardware reset or software reset.
I/O/T PCI address and data bus.
I/O/T PCI byte enables.
I/O/T PCI frame signal. Used by PCI initiators for signalling the beginning and end of a PCI
transaction.
I/O/T PCI initiator ready signal.
I/O/T PCI target ready signal.
I/O/T PCI device select signal. Asserted by targets of PCI transactions to claim the transaction.
I/O/T PCI stop signal.
I/O/T PCI parity error signal.
I/O/T PCI parity signal.
O PCI request signal. Used for requesting the use of the PCI bus.
I/O/T PCI system error signal. Requires a pull-up on the system board.
I/O/T PCI reset signal.
I
PCI grant signal. Used for granting access to the PCI bus.
I
PCI initialization device select signal. Individual device selects for targets of PCI config-
uration transactions.
I
PCI lock signal. Used to lock a target or the entire PCI bus for use by the master that
asserts the lock.
I
PCI clock.
I/O/T PCI interrupt A line on PCI bus. Asserted by the ADSP-BF535 Blackfin processor as a
device-to-signal an interrupt to the system processor. Monitored by the ADSP-BF535
when acting as the system processor.
I
PCI interrupt B line. Monitored by ADSP-BF535 Blackfin processor when acting as the
system processor.
I
PCI interrupt C line. Monitored by the ADSP-BF535 Blackfin processor when acting as
the system processor.
I
PCI interrupt D line. Monitored by the ADSP-BF535 Blackfin processor when acting as
the system processor.
I
Real-Time Clock oscillator input.
O Real-Time Clock oscillator output.
O Emulator acknowledge, open drain. Must be connected to the ADSP-BF535 Blackfin
processor emulator target board connector only.
P PLL power supply (1.5 V nominal).
P Real-Time Clock power supply (3.3 V nominal).
P I/O (except PCI) power supply (3.3 V nominal).
P PCI I/O power supply (3.3 V nominal).
P Internal power supply (1.5 V nominal).
G Power supply return.
Type column symbols: G = Ground, I = Input, O = Output, P = Power supply, T = Three-state
REV. A
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