ADSP-BF535 Datasheet, PDF (17/44 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF535
PIN DESCRIPTIONS
ADSP-BF535 Blackfin processor pin definitions are listed in
Table 7. The following pins are asynchronous: ARDY, PF15–0,
USB_CLK, NMI, TRST, RESET, PCI_CLK, XTALI,
XTALO.
Table 7. Pin Descriptions
Pin
Type Function
ADDR25 – 2
O/T External address bus.
DATA31 – 0
I/O/T External data bus. (Pin has a logic-level hold circuit that prevents the input from floating
ABE3–0/SDQM3 – 0
AMS3–0
internally.)
O/T Asynchronous memory byte enables SDRAM data masks.
O/T Chip selects for asynchronous memories.
ARDY¹
AOE
ARE
I
Acknowledge signal for asynchronous memories.
O/T Memory output enable for asynchronous memories.
O Read enable for asynchronous memories.
AWE
O Write enable for asynchronous memories.
CLKOUT/SCLK1
O SDRAM clock output pin. Same frequency and timing as SCLK0. Provided to reduce
capacitance loading on SCLK0. Connect to SDRAM’s CK pin.
SCLK0
O SDRAM clock output pin 0. Switches at system clock frequency. Connect to the
SDRAM’s CK pin.
SCKE
O/T SDRAM clock enable pin. Connect to SDRAM’s CKE pin.
SA10
O/T SDRAM A10 pin. SDRAM interface uses this pin to retain control of the SDRAM device
during host bus requests. Connect to SDRAM’s A10 pin.
SRAS
O/T SDRAM row address strobe pin. Connect to SDRAM’s RAS pin.
SCAS
O/T SDRAM column address select pin. Connect to SDRAM’s CAS pin.
SWE
O/T SDRAM write enable pin. Connect to SDRAM’s WE or W buffer pin.
SMS3–0
O/T Memory select pin of external memory bank configured for SDRAM. Connect to
SDRAM’s chip select pin.
TMR0
I/O/T Timer 0 pin. Functions as an output pin in PWMOUT mode and as an input pin in
WIDTH_CNT and EXT_CLK modes.
TMR1
I/O/T Timer 1 pin. Functions as an output pin in PWMOUT mode and as an input pin in
WIDTH_CNT and EXT_CLK modes.
TMR2
I/O/T Timer 2 pin. Functions as an output pin in PWMOUT mode and as an input pin in
PF15/SPI1SEL7
PF14/SPI0SEL7
PF13/SPI1SEL6
PF12/SPI0SEL6
PF11/SPI1SEL5
PF10/SPI0SEL5
WIDTH_CNT and EXT_CLK modes.
I/O/T Programmable flag pin. SPI output select pin.
I/O/T Programmable flag pin. SPI output select pin.
I/O/T Programmable flag pin. SPI output select pin.
I/O/T Programmable flag pin. SPI output select pin.
I/O/T Programmable flag pin. SPI output select pin.
I/O/T Programmable flag pin. SPI output select pin (used during SPI boot).
PF9/SPI1SEL4/SSEL1 I/O Programmable flag pin. SPI output select pin. Sampled during reset to determine core
clock to system clock ratio.
PF8/SPI0SEL4/SSEL0 I/O Programmable flag pin. SPI output select pin. Sampled during reset to determine core
PF7/SPI1SEL3/DF
clock to system clock ratio.
I/O Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. DF = 1 is for high frequency clock and divides
the input clock by 2. DF = 0 passes input clock directly to PLL phase detector.
PF6/SPI0SEL3/MSEL6 I/O Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF5/SPI1SEL2/MSEL5 I/O Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
Type column symbols: G = Ground, I = Input, O = Output, P = Power supply, T = Three-state
REV. A
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