ADSP-BF532_15 Datasheet, PDF (19/64 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 9. Pin Descriptions (Continued)
Pin Name
Type Function
Driver
Type¹
RFS1
I/O SPORT1 Receive Frame Sync
C
DR1PRI
I SPORT1 Receive Data Primary
DR1SEC
I SPORT1 Receive Data Secondary
TSCLK1
I/O SPORT1 Transmit Serial Clock
D
TFS1
I/O SPORT1 Transmit Frame Sync
C
DT1PRI
O SPORT1 Transmit Data Primary
C
DT1SEC
O SPORT1 Transmit Data Secondary
C
UART Port
RX
I UART Receive
TX
O UART Transmit
C
Real-Time Clock
RTXI
I RTC Crystal Input (This pin should be pulled low when not used.)
RTXO
O RTC Crystal Output (Does not three-state in hibernate.)
Clock
CLKIN
I Clock/Crystal Input (This pin needs to be at a level or clocking.)
XTAL
O Crystal Output
Mode Controls
RESET
I Reset (This pin is always active during core power-on.)
NMI
I Nonmaskable Interrupt (This pin should be pulled low when not used.)
BMODE1–0
I Boot Mode Strap (These pins must be pulled to the state required for the desired boot mode.)
Voltage Regulator
VROUT1–0
O External FET Drive (These pins should be left unconnected when unused and are driven high
during hibernate.)
Supplies
V_DDEXT
V_DDINT
V_DDRTC
P I/O Power Supply
P Core Power Supply
P Real-Time Clock Power Supply (This pin should be connected to V_DDEXT when not used and should
remain powered at all times.)
GND
G External Ground
1 _{Refer to Figure 33 on Page 43 to Figure 44 on Page 44.}
Rev. I | Page 19 of 64 | August 2013