AD9549 Datasheet, PDF (19/78 Pages) Analog Devices – Dual Input Network Clock Generator/Synchronizer

Preliminary Technical Data
AD9549
12
I
13
I
14, 37, 46, I
47, 49
15
I
16
I
17, 18
20, 21
22
O
27
I
28
I
31
32
I
33, 39, 43, I
52
34
O
35
O
38
O
40
I
41
I
48
O
50
O
51
O
56
I/O
57
I/O
58
I
59
I
60
I
Diff
Input
Diff
Input
Power
REFA_IN
REFA_INB
AVDD3
Frequency/Phase Reference A Input. This internally biased input is typically AC-coupled,
and when configured as such, can accept any differential signal.
Complementary Frequency/Phase Reference A Input: Complementary signal to the
input provided on pin 12
Analog Supply: Connect to a nominal 3.3V supply
REFB_IN
REFB_INB
N/C
PFD_VRB,
PFD_VRT
I set PFD_RSET
Res
SYSCLK
SYSCLKB
LOOP_FILTER
1.8V CLKMODESEL
CMOS
GND AVSS
Frequency/Phase Reference B Input. This internally biased input is typically AC-coupled,
and when configured as such, can accept any differential signal whose single-ended
swing is between 0.4 and 3.3V.
Complementary Frequency/Phase Reference B Input: Complementary signal to the input
provided on pin 15
No Connects: These are excess, unused pins that may be left floating
These pins must be capacitively decoupled. See the Phase Detector Pin Connections
section for details.
Connect a 5kΩ resistor from this pin to Ground
(see the Phase Detector Pin Connections section).
System Clock Input
Complementary System Clock: Complementary signal to the input provided on pin 27
System Clock Multiplier Loop Filter: When using the frequency multiplier to drive the
System Clock, an external loop filter must be constructed and attached to this pin.
Clock Mode Select. Set to GND when using a crystal. Pull up to 1.8V when using either an
oscillator or external clock source. (See the SysClk Inputs section for details on the use of
this pin).
Analog Ground: Connect to Ground. NOTE: Pin 43 is a ground shield connection.
1.8V
HSTL
1.8V
HSTL
3.3V
CMOS
OUTB
OUT
OUT_CMOS
FDBK_INB
FDBK_IN
DAC_RSET
IOUT
IOUTB
3.3V REFSELECT
CMOS
3.3V
CMOS
3.3V
CMOS
3.3V
CMOS
HOLDOVER
PWRDOWN
RESET
3.3V IO_UPDATE
Complementary HSTL Output: See spec table and the OUTPUT DRIVERS AND
MULTIPLIER section, under sub heading Primary (Differential) Driver, for details
HSTL Output: See specification table and the CLOCK DRIVERS section
CMOS Output: See specification table and the CLOCK DRIVERS section
Complementary Feedback input: In standard operating mode, this pin is connected to
the filtered IOUTB output . This internally biased input is typically AC-coupled, and when
configured as such, can accept any differential signal.
Feedback Input: In standard operating mode, this pin is connected to the filtered IOUT
output
DAC output current setting resistor. Connect a resistor from this pin to GND . See the
“DAC Output” section.
DAC output: Output signal should be filtered and sent back on chip through FDBK_INB
input
Complimentary DAC output: Output signal should be filtered and sent back on chip
through FDBK_IN input
Reference Select input: In manual mode, the REFSELECT pin operates as a high
impedance input pin, while in automatic mode, it operates as a low impedance output
pin. Logic 0 (low) indicates/selects RefA. Logic 1 (high) indicates/selects RefB.
Holdover: (Active high) In manual holdover mode, this pin is used to force the AD9549
into holdover mode. In automatic holdover mode, it indicates holdover status.
Power Down: When this active high pin is asserted, the device becomes inactive and
enters a low power state.
Chip Reset: When this active high pin is asserted, the chip goes into reset. Note: upon
power up, a 10 us reset pulse is automatically generated when the power supplies reach
a threshold and stabilize.
I/O Update: A logic transition from 0 to 1 on this pin transfers data from the I/O port
Rev. PrA | Page 19 of 78