AD9389 Datasheet, PDF (19/48 Pages) Analog Devices – 800 MHz High Performance HDMI/DVI Transmitter

HDCP HANDLING
The AD9389 has a built-in microcontroller to handle HDCP
transmitter states, including handling downstream HDCP
repeaters. To activate HDCP from a system level, the main
controller needs to set 0xAF[7] to 1 to inform AD9389 that the
video stream should be encrypted. The AD9389 takes control
from there, and implements all remaining tasks defined by the
HDCP 1.1 specification.
The system controller should monitor the status of HDCP by
reading Register 0xB8[6] (indicating the HDCP link has been
established). There are also some error flags (0xC5[7] and
0xC8[7:4]) to help debug the system.
The AD9389 also supports AV functions to suspend HDCP
temporarily. To set AV mute, clear 0x45[7] and set 0x45[6]
to 1. To clear AV mute, clear 0x45[6] and set 0x45[7] to 1. (Note
that it is invalid to set the two mute bits at the same time.)
For more information, refer to application note AN-810, EDID
and HDCP Controller User Guide for the AD9889.
EDID READING
The AD9389 has an I²C master (DDC Pin 44 and Pin 45) to
read the EDID based on system need. It buffers segment 0 once
HPD is detected. The system can request other segments by
programming Register 0xC4. An interrupt bit (0x96[2])
indicates the completion of EDID rebuffering.
To read the EDID data from the AD9389, use the AD9389
programming bus (Pin 46 and Pin 47) with I²C Address 0x7E.
This is the default address but can be changed by writing the
desired address into Register 0x43.
For more information, refer to Application Note AN-810, EDID
and HDCP Controller User Guide for the AD9889.
AD9389
INTERRUPTS
The AD9389 has interrupts to help with the system design: hot
plug detection, receiver sense, VS detection, audio FIFO
overflow, ITU 656 error, EDID ready, HDCP error, and BKSV
ready. Interrupts can be cleared by writing 1 into the interrupt
register (0x96, 0x97). There are read-only registers (0xC5,
0xC6) to show the state of these signals. Masks (0x94, 0x95) are
available to let the user selectively activate each interrupt. To
enable a specific interrupt register, write 1 to the corresponding
mask bit.
POWER MANAGEMENT
The AD9389 power-down pin polarity depends on the
AD9389’s I²C address selection. To use 0x72, the PD pin is high
active. To use 0x7A, the PD pin is low active. The power-down
pin polarity can be verified by reading Register 0x42[7].
The AD9389 can be powered down or reset either by Pin 33 or
by Register 0x41[6]. During power-down mode, all the circuits
are inactive except the I²C slave and some circuits related to
mode and activity detection. During power-down mode, the
chip status can still be read through the I²C slave. To enter
normal power-down mode, either drive Pin 33 to 1, or set
0x41[6] to 1. To further reduce power consumption, disable the
receiver sense detection by setting Register 0xA4[2] to 1.
For HDCP security reasons, the I²C power-down bit is also
reset by the power-down pin. Anytime after power down, the
user needs to drive the PD pin back to 0, and set 0x41[6] to
0 to activate the chip.
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